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https://github.com/Ryujinx/Ryujinx.git
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5e0f8e8738
* Implement JIT Arm64 backend * PPTC version bump * Address some feedback from Arm64 JIT PR * Address even more PR feedback * Remove unused IsPageAligned function * Sync Qc flag before calls * Fix comment and remove unused enum * Address riperiperi PR feedback * Delete Breakpoint IR instruction that was only implemented for Arm64
50 lines
1.7 KiB
C#
50 lines
1.7 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using System;
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namespace ARMeilleure.CodeGen.RegisterAllocators
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{
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readonly struct RegisterMasks
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{
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public int IntAvailableRegisters { get; }
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public int VecAvailableRegisters { get; }
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public int IntCallerSavedRegisters { get; }
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public int VecCallerSavedRegisters { get; }
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public int IntCalleeSavedRegisters { get; }
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public int VecCalleeSavedRegisters { get; }
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public int RegistersCount { get; }
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public RegisterMasks(
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int intAvailableRegisters,
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int vecAvailableRegisters,
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int intCallerSavedRegisters,
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int vecCallerSavedRegisters,
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int intCalleeSavedRegisters,
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int vecCalleeSavedRegisters,
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int registersCount)
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{
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IntAvailableRegisters = intAvailableRegisters;
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VecAvailableRegisters = vecAvailableRegisters;
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IntCallerSavedRegisters = intCallerSavedRegisters;
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VecCallerSavedRegisters = vecCallerSavedRegisters;
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IntCalleeSavedRegisters = intCalleeSavedRegisters;
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VecCalleeSavedRegisters = vecCalleeSavedRegisters;
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RegistersCount = registersCount;
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}
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public int GetAvailableRegisters(RegisterType type)
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{
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if (type == RegisterType.Integer)
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{
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return IntAvailableRegisters;
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}
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else if (type == RegisterType.Vector)
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{
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return VecAvailableRegisters;
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}
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else
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{
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throw new ArgumentException($"Invalid register type \"{type}\".");
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}
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}
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}
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} |