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Ryujinx/ChocolArm64/Instruction
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LDj3SNuD d021d5dfa9 Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) 
* Create CpuTestSimdCrypto.cs

* Update AOpCodeTable.cs

* Create AInstEmitSimdCrypto.cs

* Update ASoftFallback.cs

* Create ACryptoHelper.cs
2018-08-20 01:20:26 -03:00
..
ACryptoHelper.cs Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) 2018-08-20 01:20:26 -03:00
AInst.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
AInstEmitAlu.cs Remove broken adds/cmn with condition check optimization (#218) 2018-07-03 21:54:05 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs Implement SvcGetThreadContext3 2018-06-26 01:10:15 -03:00
AInstEmitFlow.cs Stub a few services, add support for generating call stacks on the CPU 2018-04-22 01:22:46 -03:00
AInstEmitHash.cs Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) 2018-06-25 22:32:29 -03:00
AInstEmitMemory.cs Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code 2018-06-02 11:44:52 -03:00
AInstEmitMemoryEx.cs Fix load/store exclusive/atomic pairwise instructions (#337) 2018-08-10 01:14:27 -03:00
AInstEmitMemoryHelper.cs More flexible memory manager (#307) 2018-08-15 15:59:51 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273) 2018-08-14 23:54:12 -03:00
AInstEmitSimdCmp.cs Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273) 2018-08-14 23:54:12 -03:00
AInstEmitSimdCrypto.cs Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) 2018-08-20 01:20:26 -03:00
AInstEmitSimdCvt.cs Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) 2018-07-14 13:13:02 -03:00
AInstEmitSimdHash.cs Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352) 2018-08-16 21:44:44 -03:00
AInstEmitSimdHelper.cs Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273) 2018-08-14 23:54:12 -03:00
AInstEmitSimdLogical.cs Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) 2018-07-14 13:13:02 -03:00
AInstEmitSimdMemory.cs Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) 2018-07-14 13:13:02 -03:00
AInstEmitSimdMove.cs Implement Ssubw_V and Usubw_V instructions. (#287) 2018-07-18 21:06:28 -03:00
AInstEmitSimdShift.cs Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) 2018-07-14 13:13:02 -03:00
AInstEmitSystem.cs
AInstEmitter.cs
AInstInterpreter.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
ASoftFallback.cs Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) 2018-08-20 01:20:26 -03:00
ASoftFloat.cs Fix silly copy/paste error on float variant of the FMINNM instruction 2018-08-05 18:56:30 -03:00
AVectorHelper.cs Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273) 2018-08-14 23:54:12 -03:00