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https://github.com/Ryujinx/Ryujinx.git
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c8bb3cc50e
* Fix register read after write on STREX implementation * PTC version update
198 lines
7.5 KiB
C#
198 lines
7.5 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitMemoryExHelper
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{
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private const int ErgSizeLog2 = 4;
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public static Operand EmitLoadExclusive(ArmEmitterContext context, Operand address, bool exclusive, int size)
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{
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if (exclusive)
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{
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Operand value;
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if (size == 4)
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{
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Operand isUnalignedAddr = InstEmitMemoryHelper.EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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context.MarkLabel(lblFastPath);
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// Only 128-bit CAS is guaranteed to have a atomic load.
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Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, null, write: false);
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Operand zero = context.VectorZero();
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value = context.CompareAndSwap(physAddr, zero, zero);
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}
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else
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{
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value = InstEmitMemoryHelper.EmitReadIntAligned(context, address, size);
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}
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset()));
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context.Store(exAddrPtr, context.BitwiseAnd(address, Const(address.Type, GetExclusiveAddressMask())));
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// Make sure the unused higher bits of the value are cleared.
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if (size < 3)
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{
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context.Store(exValuePtr, Const(0UL));
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}
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if (size < 4)
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{
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context.Store(context.Add(exValuePtr, Const(exValuePtr.Type, 8L)), Const(0UL));
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}
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// Store the new exclusive value.
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context.Store(exValuePtr, value);
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return value;
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}
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else
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{
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return InstEmitMemoryHelper.EmitReadIntAligned(context, address, size);
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}
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}
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public static void EmitStoreExclusive(
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ArmEmitterContext context,
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Operand address,
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Operand value,
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bool exclusive,
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int size,
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int rs,
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bool a32)
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{
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if (size < 3)
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{
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value = context.ConvertI64ToI32(value);
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}
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if (exclusive)
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{
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// We overwrite one of the register (Rs),
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// keep a copy of the values to ensure we are working with the correct values.
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address = context.Copy(address);
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value = context.Copy(value);
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void SetRs(Operand value)
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{
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if (a32)
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{
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SetIntA32(context, rs, value);
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}
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else
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{
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SetIntOrZR(context, rs, value);
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}
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}
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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Operand exAddr = context.Load(address.Type, exAddrPtr);
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// STEP 1: Check if we have exclusive access to this memory region. If not, fail and skip store.
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Operand maskedAddress = context.BitwiseAnd(address, Const(address.Type, GetExclusiveAddressMask()));
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Operand exFailed = context.ICompareNotEqual(exAddr, maskedAddress);
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Operand lblExit = Label();
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SetRs(Const(1));
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context.BranchIfTrue(lblExit, exFailed);
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// STEP 2: We have exclusive access, make sure that the address is valid.
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Operand isUnalignedAddr = InstEmitMemoryHelper.EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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// STEP 3: We have exclusive access and the address is valid, attempt the store using CAS.
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context.MarkLabel(lblFastPath);
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Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, null, write: true);
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Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset()));
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Operand exValue = size switch
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{
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0 => context.Load8(exValuePtr),
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1 => context.Load16(exValuePtr),
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2 => context.Load(OperandType.I32, exValuePtr),
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3 => context.Load(OperandType.I64, exValuePtr),
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_ => context.Load(OperandType.V128, exValuePtr)
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};
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Operand currValue = size switch
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{
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0 => context.CompareAndSwap8(physAddr, exValue, value),
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1 => context.CompareAndSwap16(physAddr, exValue, value),
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_ => context.CompareAndSwap(physAddr, exValue, value)
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};
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// STEP 4: Check if we succeeded by comparing expected and in-memory values.
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Operand storeFailed;
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if (size == 4)
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{
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Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0);
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Operand currValueHigh = context.VectorExtract(OperandType.I64, currValue, 1);
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Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0);
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Operand exValueHigh = context.VectorExtract(OperandType.I64, exValue, 1);
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storeFailed = context.BitwiseOr(
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context.ICompareNotEqual(currValueLow, exValueLow),
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context.ICompareNotEqual(currValueHigh, exValueHigh));
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}
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else
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{
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storeFailed = context.ICompareNotEqual(currValue, exValue);
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}
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SetRs(storeFailed);
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context.MarkLabel(lblExit);
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}
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else
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{
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InstEmitMemoryHelper.EmitWriteIntAligned(context, address, value, size);
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}
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}
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public static void EmitClearExclusive(ArmEmitterContext context)
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{
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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// We store ULONG max to force any exclusive address checks to fail,
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// since this value is not aligned to the ERG mask.
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context.Store(exAddrPtr, Const(ulong.MaxValue));
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}
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private static long GetExclusiveAddressMask() => ~((4L << ErgSizeLog2) - 1);
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}
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}
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