Ryujinx/ChocolArm64/Decoders/OpCodeSimdFcond64.cs
LDj3SNuD ad00fd0244 Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)
* Update OpCodeTable.cs

* Update InstEmitSimdShift.cs

* Update SoftFallback.cs

* Update CpuTestSimdReg.cs

* Nit.

* Update SoftFallback.cs

* Update Optimizations.cs

* Update InstEmitSimdLogical.cs

* Update InstEmitSimdArithmetic.cs
2018-12-01 22:34:43 -02:00

18 lines
455 B
C#

using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeSimdFcond64 : OpCodeSimdReg64, IOpCodeCond64
{
public int Nzcv { get; private set; }
public Cond Cond { get; private set; }
public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Nzcv = (opCode >> 0) & 0xf;
Cond = (Cond)((opCode >> 12) & 0xf);
}
}
}