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d92fff541b
* Replace CacheResourceWrite with more general "precise" write The goal of CacheResourceWrite was to notify GPU resources when they were modified directly, by looking up the modified address/size in a structure and calling a method on each resource. The downside of this is that each resource cache has to be queried individually, they all have to implement their own way to do this, and it can only signal to resources using the same PhysicalMemory instance. This PR adds the ability to signal a write as "precise" on the tracking, which signals a special handler (if present) which can be used to avoid unnecessary flush actions, or maybe even more. For buffers, precise writes specifically do not flush, and instead punch a hole in the modified range list to indicate that the data on GPU has been replaced. The downside is that precise actions must ignore the page protection bits and always signal - as they need to notify the target resource to ignore the sequence number optimization. I had to reintroduce the sequence number increment after I2M, as removing it was causing issues in rabbids kingdom battle. However - all resources modified by I2M are notified directly to lower their sequence number, so the problem is likely that another unrelated resource is not being properly updated. Thankfully, doing this does not affect performance in the games I tested. This should fix regressions from #2624. Test any games that were broken by that. (RF4, rabbids kingdom battle) I've also added a sequence number increment to ThreedClass.IncrementSyncpoint, as it seems to fix buffer corruption in OpenGL homebrew. (this was a regression from removing sequence number increment from constant buffer update - another unrelated resource thing) * Add tests. * Add XML docs for GpuRegionHandle * Skip UpdateProtection if only precise actions were called This allows precise actions to skip reprotection costs.
706 lines
24 KiB
C#
706 lines
24 KiB
C#
using ARMeilleure.Memory;
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using Ryujinx.Cpu.Tracking;
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using Ryujinx.Memory;
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using Ryujinx.Memory.Range;
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using Ryujinx.Memory.Tracking;
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Runtime.CompilerServices;
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using System.Threading;
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namespace Ryujinx.Cpu
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{
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/// <summary>
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/// Represents a CPU memory manager which maps guest virtual memory directly onto a host virtual region.
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/// </summary>
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public class MemoryManagerHostMapped : MemoryManagerBase, IMemoryManager, IVirtualMemoryManagerTracked
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{
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public const int PageBits = 12;
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public const int PageSize = 1 << PageBits;
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public const int PageMask = PageSize - 1;
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public const int PageToPteShift = 5; // 32 pages (2 bits each) in one ulong page table entry.
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public const ulong BlockMappedMask = 0x5555555555555555; // First bit of each table entry set.
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private enum HostMappedPtBits : ulong
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{
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Unmapped = 0,
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Mapped,
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WriteTracked,
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ReadWriteTracked,
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MappedReplicated = 0x5555555555555555,
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WriteTrackedReplicated = 0xaaaaaaaaaaaaaaaa,
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ReadWriteTrackedReplicated = ulong.MaxValue
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}
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private readonly InvalidAccessHandler _invalidAccessHandler;
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private readonly bool _unsafeMode;
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private readonly MemoryBlock _addressSpace;
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private readonly MemoryBlock _addressSpaceMirror;
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private readonly ulong _addressSpaceSize;
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private readonly MemoryEhMeilleure _memoryEh;
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private ulong[] _pageTable;
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public int AddressSpaceBits { get; }
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public IntPtr PageTablePointer => _addressSpace.Pointer;
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public MemoryManagerType Type => _unsafeMode ? MemoryManagerType.HostMappedUnsafe : MemoryManagerType.HostMapped;
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public MemoryTracking Tracking { get; }
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public event Action<ulong, ulong> UnmapEvent;
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/// <summary>
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/// Creates a new instance of the host mapped memory manager.
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/// </summary>
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/// <param name="addressSpaceSize">Size of the address space</param>
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/// <param name="unsafeMode">True if unmanaged access should not be masked (unsafe), false otherwise.</param>
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/// <param name="invalidAccessHandler">Optional function to handle invalid memory accesses</param>
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public MemoryManagerHostMapped(ulong addressSpaceSize, bool unsafeMode, InvalidAccessHandler invalidAccessHandler = null)
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{
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_invalidAccessHandler = invalidAccessHandler;
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_unsafeMode = unsafeMode;
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_addressSpaceSize = addressSpaceSize;
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ulong asSize = PageSize;
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int asBits = PageBits;
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while (asSize < addressSpaceSize)
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{
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asSize <<= 1;
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asBits++;
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}
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AddressSpaceBits = asBits;
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_pageTable = new ulong[1 << (AddressSpaceBits - (PageBits + PageToPteShift))];
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_addressSpace = new MemoryBlock(asSize, MemoryAllocationFlags.Reserve | MemoryAllocationFlags.Mirrorable);
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_addressSpaceMirror = _addressSpace.CreateMirror();
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Tracking = new MemoryTracking(this, PageSize, invalidAccessHandler);
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_memoryEh = new MemoryEhMeilleure(_addressSpace, Tracking);
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}
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/// <summary>
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/// Checks if the virtual address is part of the addressable space.
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/// </summary>
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/// <param name="va">Virtual address</param>
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/// <returns>True if the virtual address is part of the addressable space</returns>
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private bool ValidateAddress(ulong va)
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{
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return va < _addressSpaceSize;
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}
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/// <summary>
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/// Checks if the combination of virtual address and size is part of the addressable space.
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/// </summary>
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/// <param name="va">Virtual address of the range</param>
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/// <param name="size">Size of the range in bytes</param>
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/// <returns>True if the combination of virtual address and size is part of the addressable space</returns>
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private bool ValidateAddressAndSize(ulong va, ulong size)
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{
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ulong endVa = va + size;
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return endVa >= va && endVa >= size && endVa <= _addressSpaceSize;
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}
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/// <summary>
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/// Ensures the combination of virtual address and size is part of the addressable space.
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/// </summary>
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/// <param name="va">Virtual address of the range</param>
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/// <param name="size">Size of the range in bytes</param>
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/// <exception cref="InvalidMemoryRegionException">Throw when the memory region specified outside the addressable space</exception>
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private void AssertValidAddressAndSize(ulong va, ulong size)
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{
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if (!ValidateAddressAndSize(va, size))
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{
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throw new InvalidMemoryRegionException($"va=0x{va:X16}, size=0x{size:X16}");
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}
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}
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/// <summary>
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/// Ensures the combination of virtual address and size is part of the addressable space and fully mapped.
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/// </summary>
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/// <param name="va">Virtual address of the range</param>
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/// <param name="size">Size of the range in bytes</param>
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private void AssertMapped(ulong va, ulong size)
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{
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if (!ValidateAddressAndSize(va, size) || !IsRangeMappedImpl(va, size))
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{
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throw new InvalidMemoryRegionException($"Not mapped: va=0x{va:X16}, size=0x{size:X16}");
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}
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}
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/// <inheritdoc/>
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public void Map(ulong va, nuint hostAddress, ulong size)
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{
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AssertValidAddressAndSize(va, size);
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_addressSpace.Commit(va, size);
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AddMapping(va, size);
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Tracking.Map(va, size);
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}
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/// <inheritdoc/>
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public void Unmap(ulong va, ulong size)
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{
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AssertValidAddressAndSize(va, size);
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UnmapEvent?.Invoke(va, size);
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Tracking.Unmap(va, size);
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RemoveMapping(va, size);
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_addressSpace.Decommit(va, size);
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}
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/// <inheritdoc/>
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public T Read<T>(ulong va) where T : unmanaged
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{
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try
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{
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AssertMapped(va, (ulong)Unsafe.SizeOf<T>());
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return _addressSpaceMirror.Read<T>(va);
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}
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catch (InvalidMemoryRegionException)
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{
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if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
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{
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throw;
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}
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return default;
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}
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}
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/// <inheritdoc/>
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public T ReadTracked<T>(ulong va) where T : unmanaged
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{
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try
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{
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SignalMemoryTracking(va, (ulong)Unsafe.SizeOf<T>(), false);
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return Read<T>(va);
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}
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catch (InvalidMemoryRegionException)
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{
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if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
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{
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throw;
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}
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return default;
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}
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}
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/// <inheritdoc/>
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public void Read(ulong va, Span<byte> data)
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{
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try
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{
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AssertMapped(va, (ulong)data.Length);
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_addressSpaceMirror.Read(va, data);
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}
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catch (InvalidMemoryRegionException)
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{
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if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
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{
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throw;
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}
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}
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}
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/// <inheritdoc/>
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public void Write<T>(ulong va, T value) where T : unmanaged
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{
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try
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{
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SignalMemoryTracking(va, (ulong)Unsafe.SizeOf<T>(), write: true);
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_addressSpaceMirror.Write(va, value);
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}
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catch (InvalidMemoryRegionException)
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{
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if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
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{
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throw;
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}
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}
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}
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/// <inheritdoc/>
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public void Write(ulong va, ReadOnlySpan<byte> data)
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{
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try {
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SignalMemoryTracking(va, (ulong)data.Length, write: true);
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_addressSpaceMirror.Write(va, data);
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}
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catch (InvalidMemoryRegionException)
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{
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if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
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{
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throw;
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}
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}
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}
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/// <inheritdoc/>
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public void WriteUntracked(ulong va, ReadOnlySpan<byte> data)
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{
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try
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{
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AssertMapped(va, (ulong)data.Length);
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_addressSpaceMirror.Write(va, data);
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}
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catch (InvalidMemoryRegionException)
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{
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if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
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{
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throw;
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}
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}
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}
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/// <inheritdoc/>
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public ReadOnlySpan<byte> GetSpan(ulong va, int size, bool tracked = false)
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{
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if (tracked)
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{
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SignalMemoryTracking(va, (ulong)size, write: false);
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}
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else
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{
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AssertMapped(va, (ulong)size);
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}
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return _addressSpaceMirror.GetSpan(va, size);
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}
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/// <inheritdoc/>
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public WritableRegion GetWritableRegion(ulong va, int size, bool tracked = false)
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{
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if (tracked)
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{
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SignalMemoryTracking(va, (ulong)size, true);
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}
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else
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{
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AssertMapped(va, (ulong)size);
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}
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return _addressSpaceMirror.GetWritableRegion(va, size);
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}
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/// <inheritdoc/>
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public ref T GetRef<T>(ulong va) where T : unmanaged
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{
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SignalMemoryTracking(va, (ulong)Unsafe.SizeOf<T>(), true);
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return ref _addressSpaceMirror.GetRef<T>(va);
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}
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/// <inheritdoc/>
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public bool IsMapped(ulong va)
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{
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return ValidateAddress(va) && IsMappedImpl(va);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private bool IsMappedImpl(ulong va)
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{
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ulong page = va >> PageBits;
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int bit = (int)((page & 31) << 1);
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int pageIndex = (int)(page >> PageToPteShift);
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ref ulong pageRef = ref _pageTable[pageIndex];
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ulong pte = Volatile.Read(ref pageRef);
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return ((pte >> bit) & 3) != 0;
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}
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/// <inheritdoc/>
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public bool IsRangeMapped(ulong va, ulong size)
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{
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AssertValidAddressAndSize(va, size);
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return IsRangeMappedImpl(va, size);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void GetPageBlockRange(ulong pageStart, ulong pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex)
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{
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startMask = ulong.MaxValue << ((int)(pageStart & 31) << 1);
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endMask = ulong.MaxValue >> (64 - ((int)(pageEnd & 31) << 1));
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pageIndex = (int)(pageStart >> PageToPteShift);
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pageEndIndex = (int)((pageEnd - 1) >> PageToPteShift);
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}
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private bool IsRangeMappedImpl(ulong va, ulong size)
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{
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int pages = GetPagesCount(va, size, out _);
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if (pages == 1)
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{
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return IsMappedImpl(va);
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}
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ulong pageStart = va >> PageBits;
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ulong pageEnd = pageStart + (ulong)pages;
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GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
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// Check if either bit in each 2 bit page entry is set.
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// OR the block with itself shifted down by 1, and check the first bit of each entry.
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ulong mask = BlockMappedMask & startMask;
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while (pageIndex <= pageEndIndex)
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{
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if (pageIndex == pageEndIndex)
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{
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mask &= endMask;
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}
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ref ulong pageRef = ref _pageTable[pageIndex++];
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ulong pte = Volatile.Read(ref pageRef);
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pte |= pte >> 1;
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if ((pte & mask) != mask)
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{
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return false;
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}
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mask = BlockMappedMask;
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}
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return true;
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}
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/// <inheritdoc/>
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public IEnumerable<HostMemoryRange> GetPhysicalRegions(ulong va, ulong size)
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{
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if (size == 0)
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{
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return Enumerable.Empty<HostMemoryRange>();
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}
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AssertMapped(va, size);
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return new HostMemoryRange[] { new HostMemoryRange(_addressSpaceMirror.GetPointer(va, size), size) };
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}
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/// <inheritdoc/>
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/// <remarks>
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/// This function also validates that the given range is both valid and mapped, and will throw if it is not.
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/// </remarks>
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public void SignalMemoryTracking(ulong va, ulong size, bool write, bool precise = false)
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{
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AssertValidAddressAndSize(va, size);
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if (precise)
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{
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Tracking.VirtualMemoryEvent(va, size, write, precise: true);
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return;
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}
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// Software table, used for managed memory tracking.
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int pages = GetPagesCount(va, size, out _);
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ulong pageStart = va >> PageBits;
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if (pages == 1)
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{
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ulong tag = (ulong)(write ? HostMappedPtBits.WriteTracked : HostMappedPtBits.ReadWriteTracked);
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int bit = (int)((pageStart & 31) << 1);
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int pageIndex = (int)(pageStart >> PageToPteShift);
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ref ulong pageRef = ref _pageTable[pageIndex];
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ulong pte = Volatile.Read(ref pageRef);
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ulong state = ((pte >> bit) & 3);
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if (state >= tag)
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{
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Tracking.VirtualMemoryEvent(va, size, write);
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return;
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}
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else if (state == 0)
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{
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ThrowInvalidMemoryRegionException($"Not mapped: va=0x{va:X16}, size=0x{size:X16}");
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}
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}
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else
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{
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ulong pageEnd = pageStart + (ulong)pages;
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GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
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ulong mask = startMask;
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ulong anyTrackingTag = (ulong)HostMappedPtBits.WriteTrackedReplicated;
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while (pageIndex <= pageEndIndex)
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{
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if (pageIndex == pageEndIndex)
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{
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mask &= endMask;
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}
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ref ulong pageRef = ref _pageTable[pageIndex++];
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ulong pte = Volatile.Read(ref pageRef);
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ulong mappedMask = mask & BlockMappedMask;
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ulong mappedPte = pte | (pte >> 1);
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if ((mappedPte & mappedMask) != mappedMask)
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{
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ThrowInvalidMemoryRegionException($"Not mapped: va=0x{va:X16}, size=0x{size:X16}");
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}
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pte &= mask;
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if ((pte & anyTrackingTag) != 0) // Search for any tracking.
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{
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// Writes trigger any tracking.
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// Only trigger tracking from reads if both bits are set on any page.
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if (write || (pte & (pte >> 1) & BlockMappedMask) != 0)
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{
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Tracking.VirtualMemoryEvent(va, size, write);
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break;
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}
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}
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mask = ulong.MaxValue;
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}
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}
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}
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/// <summary>
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/// Computes the number of pages in a virtual address range.
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/// </summary>
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/// <param name="va">Virtual address of the range</param>
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/// <param name="size">Size of the range</param>
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/// <param name="startVa">The virtual address of the beginning of the first page</param>
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/// <remarks>This function does not differentiate between allocated and unallocated pages.</remarks>
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private int GetPagesCount(ulong va, ulong size, out ulong startVa)
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{
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// WARNING: Always check if ulong does not overflow during the operations.
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startVa = va & ~(ulong)PageMask;
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ulong vaSpan = (va - startVa + size + PageMask) & ~(ulong)PageMask;
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return (int)(vaSpan / PageSize);
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}
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/// <inheritdoc/>
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public void TrackingReprotect(ulong va, ulong size, MemoryPermission protection)
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{
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// Protection is inverted on software pages, since the default value is 0.
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protection = (~protection) & MemoryPermission.ReadAndWrite;
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int pages = GetPagesCount(va, size, out va);
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ulong pageStart = va >> PageBits;
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if (pages == 1)
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{
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ulong protTag = protection switch
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{
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MemoryPermission.None => (ulong)HostMappedPtBits.Mapped,
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MemoryPermission.Write => (ulong)HostMappedPtBits.WriteTracked,
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_ => (ulong)HostMappedPtBits.ReadWriteTracked,
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};
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int bit = (int)((pageStart & 31) << 1);
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ulong tagMask = 3UL << bit;
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ulong invTagMask = ~tagMask;
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ulong tag = protTag << bit;
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int pageIndex = (int)(pageStart >> PageToPteShift);
|
|
ref ulong pageRef = ref _pageTable[pageIndex];
|
|
|
|
ulong pte;
|
|
|
|
do
|
|
{
|
|
pte = Volatile.Read(ref pageRef);
|
|
}
|
|
while ((pte & tagMask) != 0 && Interlocked.CompareExchange(ref pageRef, (pte & invTagMask) | tag, pte) != pte);
|
|
}
|
|
else
|
|
{
|
|
ulong pageEnd = pageStart + (ulong)pages;
|
|
|
|
GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
|
|
|
|
ulong mask = startMask;
|
|
|
|
ulong protTag = protection switch
|
|
{
|
|
MemoryPermission.None => (ulong)HostMappedPtBits.MappedReplicated,
|
|
MemoryPermission.Write => (ulong)HostMappedPtBits.WriteTrackedReplicated,
|
|
_ => (ulong)HostMappedPtBits.ReadWriteTrackedReplicated,
|
|
};
|
|
|
|
while (pageIndex <= pageEndIndex)
|
|
{
|
|
if (pageIndex == pageEndIndex)
|
|
{
|
|
mask &= endMask;
|
|
}
|
|
|
|
ref ulong pageRef = ref _pageTable[pageIndex++];
|
|
|
|
ulong pte;
|
|
ulong mappedMask;
|
|
|
|
// Change the protection of all 2 bit entries that are mapped.
|
|
do
|
|
{
|
|
pte = Volatile.Read(ref pageRef);
|
|
|
|
mappedMask = pte | (pte >> 1);
|
|
mappedMask |= (mappedMask & BlockMappedMask) << 1;
|
|
mappedMask &= mask; // Only update mapped pages within the given range.
|
|
}
|
|
while (Interlocked.CompareExchange(ref pageRef, (pte & (~mappedMask)) | (protTag & mappedMask), pte) != pte);
|
|
|
|
mask = ulong.MaxValue;
|
|
}
|
|
}
|
|
|
|
protection = protection switch
|
|
{
|
|
MemoryPermission.None => MemoryPermission.ReadAndWrite,
|
|
MemoryPermission.Write => MemoryPermission.Read,
|
|
_ => MemoryPermission.None
|
|
};
|
|
|
|
_addressSpace.Reprotect(va, size, protection, false);
|
|
}
|
|
|
|
/// <inheritdoc/>
|
|
public CpuRegionHandle BeginTracking(ulong address, ulong size)
|
|
{
|
|
return new CpuRegionHandle(Tracking.BeginTracking(address, size));
|
|
}
|
|
|
|
/// <inheritdoc/>
|
|
public CpuMultiRegionHandle BeginGranularTracking(ulong address, ulong size, IEnumerable<IRegionHandle> handles, ulong granularity)
|
|
{
|
|
return new CpuMultiRegionHandle(Tracking.BeginGranularTracking(address, size, handles, granularity));
|
|
}
|
|
|
|
/// <inheritdoc/>
|
|
public CpuSmartMultiRegionHandle BeginSmartGranularTracking(ulong address, ulong size, ulong granularity)
|
|
{
|
|
return new CpuSmartMultiRegionHandle(Tracking.BeginSmartGranularTracking(address, size, granularity));
|
|
}
|
|
|
|
/// <summary>
|
|
/// Adds the given address mapping to the page table.
|
|
/// </summary>
|
|
/// <param name="va">Virtual memory address</param>
|
|
/// <param name="size">Size to be mapped</param>
|
|
private void AddMapping(ulong va, ulong size)
|
|
{
|
|
int pages = GetPagesCount(va, size, out _);
|
|
ulong pageStart = va >> PageBits;
|
|
ulong pageEnd = pageStart + (ulong)pages;
|
|
|
|
GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
|
|
|
|
ulong mask = startMask;
|
|
|
|
while (pageIndex <= pageEndIndex)
|
|
{
|
|
if (pageIndex == pageEndIndex)
|
|
{
|
|
mask &= endMask;
|
|
}
|
|
|
|
ref ulong pageRef = ref _pageTable[pageIndex++];
|
|
|
|
ulong pte;
|
|
ulong mappedMask;
|
|
|
|
// Map all 2-bit entries that are unmapped.
|
|
do
|
|
{
|
|
pte = Volatile.Read(ref pageRef);
|
|
|
|
mappedMask = pte | (pte >> 1);
|
|
mappedMask |= (mappedMask & BlockMappedMask) << 1;
|
|
mappedMask |= ~mask; // Treat everything outside the range as mapped, thus unchanged.
|
|
}
|
|
while (Interlocked.CompareExchange(ref pageRef, (pte & mappedMask) | (BlockMappedMask & (~mappedMask)), pte) != pte);
|
|
|
|
mask = ulong.MaxValue;
|
|
}
|
|
}
|
|
|
|
/// <summary>
|
|
/// Removes the given address mapping from the page table.
|
|
/// </summary>
|
|
/// <param name="va">Virtual memory address</param>
|
|
/// <param name="size">Size to be unmapped</param>
|
|
private void RemoveMapping(ulong va, ulong size)
|
|
{
|
|
int pages = GetPagesCount(va, size, out _);
|
|
ulong pageStart = va >> PageBits;
|
|
ulong pageEnd = pageStart + (ulong)pages;
|
|
|
|
GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
|
|
|
|
startMask = ~startMask;
|
|
endMask = ~endMask;
|
|
|
|
ulong mask = startMask;
|
|
|
|
while (pageIndex <= pageEndIndex)
|
|
{
|
|
if (pageIndex == pageEndIndex)
|
|
{
|
|
mask |= endMask;
|
|
}
|
|
|
|
ref ulong pageRef = ref _pageTable[pageIndex++];
|
|
ulong pte;
|
|
|
|
do
|
|
{
|
|
pte = Volatile.Read(ref pageRef);
|
|
}
|
|
while (Interlocked.CompareExchange(ref pageRef, pte & mask, pte) != pte);
|
|
|
|
mask = 0;
|
|
}
|
|
}
|
|
|
|
/// <summary>
|
|
/// Disposes of resources used by the memory manager.
|
|
/// </summary>
|
|
protected override void Destroy()
|
|
{
|
|
_addressSpaceMirror.Dispose();
|
|
_addressSpace.Dispose();
|
|
_memoryEh.Dispose();
|
|
}
|
|
|
|
private void ThrowInvalidMemoryRegionException(string message) => throw new InvalidMemoryRegionException(message);
|
|
}
|
|
}
|