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SDL_TriggerBreakppoint for riscv arch (both 32/64) version.
`ebreak` acts like int3 for x86, giving control of running process to debuggers. (cherry picked from commit 723bcd0a8be4e816f6555b6bbbd5e9c26ab27137)
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@ -55,6 +55,8 @@ assert can have unique static variables associated with it.
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#define SDL_TriggerBreakpoint() __builtin_debugtrap()
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#elif ( (!defined(__NACL__)) && ((defined(__GNUC__) || defined(__clang__)) && (defined(__i386__) || defined(__x86_64__))) )
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#define SDL_TriggerBreakpoint() __asm__ __volatile__ ( "int $3\n\t" )
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#elif (defined(__GNUC__) || defined(__clang__)) && defined(__riscv)
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#define SDL_TriggerBreakpoint() __asm__ __volatile__ ( "ebreak\n\t" )
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#elif ( defined(__APPLE__) && (defined(__arm64__) || defined(__aarch64__)) ) /* this might work on other ARM targets, but this is a known quantity... */
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#define SDL_TriggerBreakpoint() __asm__ __volatile__ ( "brk #22\n\t" )
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#elif defined(__APPLE__) && defined(__arm__)
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