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27 lines
1.1 KiB
Plaintext
27 lines
1.1 KiB
Plaintext
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pci-test is a device used for testing low level IO
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device implements up to two BARs: BAR0 and BAR1.
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Each BAR can be memory or IO. Guests must detect
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BAR type and act accordingly.
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Each BAR size is up to 4K bytes.
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Each BAR starts with the following header:
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typedef struct PCITestDevHdr {
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uint8_t test; <- write-only, starts a given test number
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uint8_t width_type; <- read-only, type and width of access for a given test.
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1,2,4 for byte,word or long write.
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any other value if test not supported on this BAR
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uint8_t pad0[2];
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uint32_t offset; <- read-only, offset in this BAR for a given test
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uint32_t data; <- read-only, data to use for a given test
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uint32_t count; <- for debugging. number of writes detected.
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uint8_t name[]; <- for debugging. 0-terminated ASCII string.
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} PCITestDevHdr;
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All registers are little endian.
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device is expected to always implement tests 0 to N on each BAR, and to add new
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tests with higher numbers. In this way a guest can scan test numbers until it
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detects an access type that it does not support on this BAR, then stop.
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