unicorn/qemu/target/riscv/cpu_user.h

#define xRA 1   /* return address (aka link register) */
#define xSP 2   /* stack pointer */
#define xGP 3   /* global pointer */
#define xTP 4   /* thread pointer */

#define xA0 10  /* gpr[10-17] are syscall arguments */
#define xA1 11
#define xA2 12
#define xA3 13
#define xA4 14
#define xA5 15
#define xA6 16
#define xA7 17  /* syscall number goes here */
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality. 2019-03-08 18:06:28 +00:00			`#define xRA 1 /* return address (aka link register) */`
			`#define xSP 2 /* stack pointer */`
			`#define xGP 3 /* global pointer */`
			`#define xTP 4 /* thread pointer */`

			`#define xA0 10 /* gpr[10-17] are syscall arguments */`
			`#define xA1 11`
			`#define xA2 12`
			`#define xA3 13`
			`#define xA4 14`
			`#define xA5 15`
			`#define xA6 16`
			`#define xA7 17 /* syscall number goes here */`