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24 lines
594 B
C
24 lines
594 B
C
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/*
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* RISC-V cpu parameters for qemu.
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*
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* Copyright (c) 2017-2018 SiFive, Inc.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef RISCV_CPU_PARAM_H
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#define RISCV_CPU_PARAM_H 1
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#if defined(TARGET_RISCV64)
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# define TARGET_LONG_BITS 64
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# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
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# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
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#elif defined(TARGET_RISCV32)
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# define TARGET_LONG_BITS 32
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# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
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# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
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#endif
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#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
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#define NB_MMU_MODES 4
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#endif
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