unicorn/qemu/target/riscv/cpu-param.h

/*
 * RISC-V cpu parameters for qemu.
 *
 * Copyright (c) 2017-2018 SiFive, Inc.
 * SPDX-License-Identifier: GPL-2.0+
 */

#ifndef RISCV_CPU_PARAM_H
#define RISCV_CPU_PARAM_H 1

#if defined(TARGET_RISCV64)
# define TARGET_LONG_BITS 64
# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
#elif defined(TARGET_RISCV32)
# define TARGET_LONG_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
#define NB_MMU_MODES 4

#endif
tcg: Split out target/arch/cpu-param.h For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Backports commit 74433bf083b0766aba81534f92de13194f23ff3e from qemu 2019-06-10 23:15:41 +00:00			`/*`
			`* RISC-V cpu parameters for qemu.`
			`*`
			`* Copyright (c) 2017-2018 SiFive, Inc.`
			`* SPDX-License-Identifier: GPL-2.0+`
			`*/`

			`#ifndef RISCV_CPU_PARAM_H`
			`#define RISCV_CPU_PARAM_H 1`

			`#if defined(TARGET_RISCV64)`
			`# define TARGET_LONG_BITS 64`
			`# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */`
			`# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */`
			`#elif defined(TARGET_RISCV32)`
			`# define TARGET_LONG_BITS 32`
			`# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */`
			`# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */`
			`#endif`
			`#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */`
			`#define NB_MMU_MODES 4`

			`#endif`