2015-08-21 07:04:50 +00:00
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/*
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* Optimizations for Tiny Code Generator for QEMU
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*
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* Copyright (c) 2010 Samsung Electronics.
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* Contributed by Kirill Batuzov <batuzovk@ispras.ru>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "config.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include "qemu-common.h"
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#include "tcg-op.h"
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#define CASE_OP_32_64(x) \
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glue(glue(case INDEX_op_, x), _i32): \
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glue(glue(case INDEX_op_, x), _i64)
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2018-02-11 03:05:19 +00:00
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static inline bool temp_is_const(TCGContext *s, TCGArg arg)
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{
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struct tcg_temp_info *temps = s->temps2;
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2018-02-11 03:11:15 +00:00
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return temps[arg].is_const;
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2018-02-11 03:05:19 +00:00
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}
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static inline bool temp_is_copy(TCGContext *s, TCGArg arg)
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{
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struct tcg_temp_info *temps = s->temps2;
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2018-02-11 03:11:15 +00:00
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return temps[arg].next_copy != arg;
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2018-02-11 03:05:19 +00:00
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}
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2018-02-11 03:11:15 +00:00
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/* Reset TEMP's state, possibly removing the temp for the list of copies. */
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2015-08-21 07:04:50 +00:00
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static void reset_temp(TCGContext *s, TCGArg temp)
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{
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struct tcg_temp_info *temps = s->temps2;
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2018-02-11 03:11:15 +00:00
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temps[temps[temp].next_copy].prev_copy = temps[temp].prev_copy;
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temps[temps[temp].prev_copy].next_copy = temps[temp].next_copy;
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temps[temp].next_copy = temp;
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temps[temp].prev_copy = temp;
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temps[temp].is_const = false;
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2015-08-21 07:04:50 +00:00
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temps[temp].mask = -1;
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}
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2018-02-11 02:46:58 +00:00
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/* Reset all temporaries, given that there are NB_TEMPS of them. */
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static void reset_all_temps(TCGContext *s, int nb_temps)
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{
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long len = BITS_TO_LONGS(nb_temps) * sizeof(unsigned long);
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memset(&s->temps2_used.l, 0, len);
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}
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/* Initialize and activate a temporary. */
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static void init_temp_info(TCGContext *s, TCGArg temp)
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{
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struct tcg_temp_info *temps = s->temps2;
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TCGTempSet *temps_used = &s->temps2_used;
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if (!test_bit(temp, temps_used->l)) {
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2018-02-11 03:11:15 +00:00
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temps[temp].next_copy = temp;
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temps[temp].prev_copy = temp;
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temps[temp].is_const = false;
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2018-02-11 02:46:58 +00:00
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temps[temp].mask = -1;
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set_bit(temp, temps_used->l);
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}
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}
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2018-02-09 18:11:19 +00:00
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static TCGOp *insert_op_before(TCGContext *s, TCGOp *old_op,
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TCGOpcode opc, int nargs)
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{
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int oi = s->gen_next_op_idx;
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int pi = s->gen_next_parm_idx;
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int prev = old_op->prev;
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int next = old_op - s->gen_op_buf;
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TCGOp *new_op;
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TCGOp new_opp = {0};
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tcg_debug_assert(oi < OPC_BUF_SIZE);
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tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
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s->gen_next_op_idx = oi + 1;
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s->gen_next_parm_idx = pi + nargs;
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new_opp.opc = opc;
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new_opp.args = pi;
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new_opp.prev = prev;
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new_opp.next = next;
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new_op = &s->gen_op_buf[oi];
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*new_op = new_opp;
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if (prev >= 0) {
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s->gen_op_buf[prev].next = oi;
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} else {
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s->gen_first_op_idx = oi;
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}
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old_op->prev = oi;
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return new_op;
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}
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2015-08-21 07:04:50 +00:00
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static int op_bits(TCGContext *s, TCGOpcode op)
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{
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const TCGOpDef *def = &s->tcg_op_defs[op];
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return def->flags & TCG_OPF_64BIT ? 64 : 32;
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}
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static TCGOpcode op_to_mov(TCGContext *s, TCGOpcode op)
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{
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switch (op_bits(s, op)) {
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case 32:
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return INDEX_op_mov_i32;
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case 64:
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return INDEX_op_mov_i64;
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default:
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fprintf(stderr, "op_to_mov: unexpected return value of "
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"function op_bits.\n");
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tcg_abort();
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}
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}
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static TCGOpcode op_to_movi(TCGContext *s, TCGOpcode op)
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{
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switch (op_bits(s, op)) {
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case 32:
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return INDEX_op_movi_i32;
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case 64:
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return INDEX_op_movi_i64;
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default:
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fprintf(stderr, "op_to_movi: unexpected return value of "
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"function op_bits.\n");
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tcg_abort();
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}
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}
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static TCGArg find_better_copy(TCGContext *s, TCGArg temp)
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{
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struct tcg_temp_info *temps = s->temps2;
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TCGArg i;
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/* If this is already a global, we can't do better. */
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2017-01-19 11:50:28 +00:00
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if (temp < (unsigned int)s->nb_globals) {
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2015-08-21 07:04:50 +00:00
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return temp;
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}
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/* Search for a global first. */
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for (i = temps[temp].next_copy ; i != temp ; i = temps[i].next_copy) {
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2017-01-19 11:50:28 +00:00
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if (i < (unsigned int)s->nb_globals) {
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2015-08-21 07:04:50 +00:00
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return i;
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}
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}
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/* If it is a temp, search for a temp local. */
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if (!s->temps[temp].temp_local) {
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for (i = temps[temp].next_copy ; i != temp ; i = temps[i].next_copy) {
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if (s->temps[i].temp_local) {
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return i;
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}
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}
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}
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/* Failure to find a better representation, return the same temp. */
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return temp;
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}
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static bool temps_are_copies(TCGContext *s, TCGArg arg1, TCGArg arg2)
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{
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struct tcg_temp_info *temps = s->temps2;
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TCGArg i;
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if (arg1 == arg2) {
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return true;
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}
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2018-02-11 03:05:19 +00:00
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if (!temp_is_copy(s, arg1) || !temp_is_copy(s, arg2)) {
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2015-08-21 07:04:50 +00:00
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return false;
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}
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for (i = temps[arg1].next_copy ; i != arg1 ; i = temps[i].next_copy) {
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if (i == arg2) {
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return true;
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}
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}
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return false;
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}
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2018-02-11 02:33:39 +00:00
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static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args,
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TCGArg dst, TCGArg val)
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{
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struct tcg_temp_info *temps = s->temps2;
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TCGOpcode new_op = op_to_movi(s, op->opc);
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tcg_target_ulong mask;
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op->opc = new_op;
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reset_temp(s, dst);
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2018-02-11 03:11:15 +00:00
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temps[dst].is_const = true;
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2018-02-11 02:33:39 +00:00
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temps[dst].val = val;
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mask = val;
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2018-02-11 02:37:49 +00:00
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if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) {
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2018-02-11 02:33:39 +00:00
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/* High bits of the destination are now garbage. */
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mask |= ~0xffffffffull;
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}
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temps[dst].mask = mask;
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args[0] = dst;
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args[1] = val;
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}
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2018-02-09 14:54:01 +00:00
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static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args,
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2018-02-11 02:23:11 +00:00
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TCGArg dst, TCGArg src)
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2015-08-21 07:04:50 +00:00
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{
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2018-02-11 02:33:39 +00:00
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if (temps_are_copies(s, dst, src)) {
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2018-02-11 02:26:43 +00:00
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tcg_op_remove(s, op);
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return;
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}
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2015-08-21 07:04:50 +00:00
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struct tcg_temp_info *temps = s->temps2;
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2018-02-11 02:23:11 +00:00
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TCGOpcode new_op = op_to_mov(s, op->opc);
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2015-08-21 07:04:50 +00:00
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tcg_target_ulong mask;
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2018-02-09 14:54:01 +00:00
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op->opc = new_op;
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2015-08-21 07:04:50 +00:00
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reset_temp(s, dst);
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mask = temps[src].mask;
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if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
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/* High bits of the destination are now garbage. */
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mask |= ~0xffffffffull;
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}
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temps[dst].mask = mask;
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if (s->temps[src].type == s->temps[dst].type) {
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temps[dst].next_copy = temps[src].next_copy;
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temps[dst].prev_copy = src;
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temps[temps[dst].next_copy].prev_copy = dst;
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temps[src].next_copy = dst;
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tcg/optimize: allow constant to have copies
Now that copies and constants are tracked separately, we can allow
constant to have copies, deferring the choice to use a register or a
constant to the register allocation pass. This prevent this kind of
regular constant reloading:
-OUT: [size=338]
+OUT: [size=298]
mov -0x4(%r14),%ebp
test %ebp,%ebp
jne 0x7ffbe9cb0ed6
mov $0x40002219f8,%rbp
mov %rbp,(%r14)
- mov $0x40002219f8,%rbp
mov $0x4000221a20,%rbx
mov %rbp,(%rbx)
mov $0x4000000000,%rbp
mov %rbp,(%r14)
- mov $0x4000000000,%rbp
mov $0x4000221d38,%rbx
mov %rbp,(%rbx)
mov $0x40002221a8,%rbp
mov %rbp,(%r14)
- mov $0x40002221a8,%rbp
mov $0x4000221d40,%rbx
mov %rbp,(%rbx)
mov $0x4000019170,%rbp
mov %rbp,(%r14)
- mov $0x4000019170,%rbp
mov $0x4000221d48,%rbx
mov %rbp,(%rbx)
mov $0x40000049ee,%rbp
mov %rbp,0x80(%r14)
mov %r14,%rdi
callq 0x7ffbe99924d0
mov $0x4000001680,%rbp
mov %rbp,0x30(%r14)
mov 0x10(%r14),%rbp
mov $0x4000001680,%rbp
mov %rbp,0x30(%r14)
mov 0x10(%r14),%rbp
shl $0x20,%rbp
mov (%r14),%rbx
mov %ebx,%ebx
mov %rbx,(%r14)
or %rbx,%rbp
mov %rbp,0x10(%r14)
mov %rbp,0x90(%r14)
mov 0x60(%r14),%rbx
mov %rbx,0x38(%r14)
mov 0x28(%r14),%rbx
mov $0x4000220e60,%r12
mov %rbx,(%r12)
mov $0x40002219c8,%rbx
mov %rbp,(%rbx)
mov 0x20(%r14),%rbp
sub $0x8,%rbp
mov $0x4000004a16,%rbx
mov %rbx,0x0(%rbp)
mov %rbp,0x20(%r14)
mov $0x19,%ebp
mov %ebp,0xa8(%r14)
mov $0x4000015110,%rbp
mov %rbp,0x80(%r14)
xor %eax,%eax
jmpq 0x7ffbebcae426
lea -0x5f6d72a(%rip),%rax # 0x7ffbe3d437b3
jmpq 0x7ffbebcae426
Backports commit 299f80130401153af1a6ddb3cc011781bcd47600 from qemu
2018-02-11 03:17:33 +00:00
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temps[dst].is_const = temps[src].is_const;
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temps[dst].val = temps[src].val;
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2015-08-21 07:04:50 +00:00
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}
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2018-02-09 14:54:01 +00:00
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args[0] = dst;
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args[1] = src;
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2015-08-21 07:04:50 +00:00
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}
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static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
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{
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uint64_t l64, h64;
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switch (op) {
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CASE_OP_32_64(add):
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return x + y;
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CASE_OP_32_64(sub):
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return x - y;
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CASE_OP_32_64(mul):
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return x * y;
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CASE_OP_32_64(and):
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return x & y;
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CASE_OP_32_64(or):
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return x | y;
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CASE_OP_32_64(xor):
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return x ^ y;
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case INDEX_op_shl_i32:
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return (uint32_t)x << (y & 31);
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case INDEX_op_shl_i64:
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return (uint64_t)x << (y & 63);
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case INDEX_op_shr_i32:
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return (uint32_t)x >> (y & 31);
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2018-02-11 03:24:03 +00:00
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case INDEX_op_trunc_shr_i64_i32:
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2015-08-21 07:04:50 +00:00
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case INDEX_op_shr_i64:
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return (uint64_t)x >> (y & 63);
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case INDEX_op_sar_i32:
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return (int32_t)x >> (y & 31);
|
|
|
|
|
|
|
|
case INDEX_op_sar_i64:
|
|
|
|
return (int64_t)x >> (y & 63);
|
|
|
|
|
|
|
|
case INDEX_op_rotr_i32:
|
|
|
|
return ror32(x, y & 31);
|
|
|
|
|
|
|
|
case INDEX_op_rotr_i64:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (TCGArg)ror64(x, y & 63);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
case INDEX_op_rotl_i32:
|
|
|
|
return rol32(x, y & 31);
|
|
|
|
|
|
|
|
case INDEX_op_rotl_i64:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (TCGArg)rol64(x, y & 63);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
CASE_OP_32_64(not):
|
|
|
|
return ~x;
|
|
|
|
|
|
|
|
CASE_OP_32_64(neg):
|
2017-01-19 11:50:28 +00:00
|
|
|
return 0-x;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
CASE_OP_32_64(andc):
|
|
|
|
return x & ~y;
|
|
|
|
|
|
|
|
CASE_OP_32_64(orc):
|
|
|
|
return x | ~y;
|
|
|
|
|
|
|
|
CASE_OP_32_64(eqv):
|
|
|
|
return ~(x ^ y);
|
|
|
|
|
|
|
|
CASE_OP_32_64(nand):
|
|
|
|
return ~(x & y);
|
|
|
|
|
|
|
|
CASE_OP_32_64(nor):
|
|
|
|
return ~(x | y);
|
|
|
|
|
|
|
|
CASE_OP_32_64(ext8s):
|
|
|
|
return (int8_t)x;
|
|
|
|
|
|
|
|
CASE_OP_32_64(ext16s):
|
|
|
|
return (int16_t)x;
|
|
|
|
|
|
|
|
CASE_OP_32_64(ext8u):
|
|
|
|
return (uint8_t)x;
|
|
|
|
|
|
|
|
CASE_OP_32_64(ext16u):
|
|
|
|
return (uint16_t)x;
|
|
|
|
|
2018-02-11 03:47:05 +00:00
|
|
|
case INDEX_op_ext_i32_i64:
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_ext32s_i64:
|
|
|
|
return (int32_t)x;
|
|
|
|
|
2018-02-11 03:47:05 +00:00
|
|
|
case INDEX_op_extu_i32_i64:
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_ext32u_i64:
|
|
|
|
return (uint32_t)x;
|
|
|
|
|
|
|
|
case INDEX_op_muluh_i32:
|
|
|
|
return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32;
|
|
|
|
case INDEX_op_mulsh_i32:
|
|
|
|
return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
|
|
|
|
|
|
|
|
case INDEX_op_muluh_i64:
|
|
|
|
mulu64(&l64, &h64, x, y);
|
2017-01-19 11:50:28 +00:00
|
|
|
return (TCGArg)h64;
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_mulsh_i64:
|
|
|
|
muls64(&l64, &h64, x, y);
|
2017-01-19 11:50:28 +00:00
|
|
|
return (TCGArg)h64;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
case INDEX_op_div_i32:
|
|
|
|
/* Avoid crashing on divide by zero, otherwise undefined. */
|
2017-01-19 11:50:28 +00:00
|
|
|
return (int32_t)x / ((int32_t)y ? (int32_t)y : 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_divu_i32:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (uint32_t)x / ((uint32_t)y ? (uint32_t)y : 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_div_i64:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (int64_t)x / ((int64_t)y ? (int64_t)y : 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_divu_i64:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (uint64_t)x / ((uint64_t)y ? (uint64_t)y : 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
case INDEX_op_rem_i32:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (int32_t)x % ((int32_t)y ? (int32_t)y : 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_remu_i32:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (uint32_t)x % ((uint32_t)y ? (uint32_t)y : 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_rem_i64:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (int64_t)x % ((int64_t)y ? (int64_t)y : 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_remu_i64:
|
2017-01-19 11:50:28 +00:00
|
|
|
return (uint64_t)x % ((uint64_t)y ? (uint64_t)y : 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
default:
|
|
|
|
fprintf(stderr,
|
|
|
|
"Unrecognized operation %d in do_constant_folding.\n", op);
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static TCGArg do_constant_folding(TCGContext *s, TCGOpcode op, TCGArg x, TCGArg y)
|
|
|
|
{
|
|
|
|
TCGArg res = do_constant_folding_2(op, x, y);
|
|
|
|
if (op_bits(s, op) == 32) {
|
tcg/optimize: fix constant signedness
By convention, on a 64-bit host TCG internally stores 32-bit constants
as sign-extended. This is not the case in the optimizer when a 32-bit
constant is folded.
This doesn't seem to have more consequences than suboptimal code
generation. For instance the x86 backend assumes sign-extended constants,
and in some rare cases uses a 32-bit unsigned immediate 0xffffffff
instead of a 8-bit signed immediate 0xff for the constant -1. This is
with a ppc guest:
before
------
---- 0x9f29cc
movi_i32 tmp1,$0xffffffff
movi_i32 tmp2,$0x0
add2_i32 tmp0,CA,CA,tmp2,r6,tmp2
add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2
mov_i32 r10,tmp0
0x7fd8c7dfe90c: xor %ebp,%ebp
0x7fd8c7dfe90e: mov %ebp,%r11d
0x7fd8c7dfe911: mov 0x18(%r14),%r9d
0x7fd8c7dfe915: add %r9d,%r10d
0x7fd8c7dfe918: adc %ebp,%r11d
0x7fd8c7dfe91b: add $0xffffffff,%r10d
0x7fd8c7dfe922: adc %ebp,%r11d
0x7fd8c7dfe925: mov %r11d,0x134(%r14)
0x7fd8c7dfe92c: mov %r10d,0x28(%r14)
after
-----
---- 0x9f29cc
movi_i32 tmp1,$0xffffffffffffffff
movi_i32 tmp2,$0x0
add2_i32 tmp0,CA,CA,tmp2,r6,tmp2
add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2
mov_i32 r10,tmp0
0x7f37010d490c: xor %ebp,%ebp
0x7f37010d490e: mov %ebp,%r11d
0x7f37010d4911: mov 0x18(%r14),%r9d
0x7f37010d4915: add %r9d,%r10d
0x7f37010d4918: adc %ebp,%r11d
0x7f37010d491b: add $0xffffffffffffffff,%r10d
0x7f37010d491f: adc %ebp,%r11d
0x7f37010d4922: mov %r11d,0x134(%r14)
0x7f37010d4929: mov %r10d,0x28(%r14)
Backports commit 29f3ff8d6cbc28f79933aeaa25805408d0984a8f from qemu
2018-02-11 02:39:52 +00:00
|
|
|
res = (int32_t)res;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c)
|
|
|
|
{
|
|
|
|
switch (c) {
|
|
|
|
case TCG_COND_EQ:
|
|
|
|
return x == y;
|
|
|
|
case TCG_COND_NE:
|
|
|
|
return x != y;
|
|
|
|
case TCG_COND_LT:
|
|
|
|
return (int32_t)x < (int32_t)y;
|
|
|
|
case TCG_COND_GE:
|
|
|
|
return (int32_t)x >= (int32_t)y;
|
|
|
|
case TCG_COND_LE:
|
|
|
|
return (int32_t)x <= (int32_t)y;
|
|
|
|
case TCG_COND_GT:
|
|
|
|
return (int32_t)x > (int32_t)y;
|
|
|
|
case TCG_COND_LTU:
|
|
|
|
return x < y;
|
|
|
|
case TCG_COND_GEU:
|
|
|
|
return x >= y;
|
|
|
|
case TCG_COND_LEU:
|
|
|
|
return x <= y;
|
|
|
|
case TCG_COND_GTU:
|
|
|
|
return x > y;
|
|
|
|
default:
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c)
|
|
|
|
{
|
|
|
|
switch (c) {
|
|
|
|
case TCG_COND_EQ:
|
|
|
|
return x == y;
|
|
|
|
case TCG_COND_NE:
|
|
|
|
return x != y;
|
|
|
|
case TCG_COND_LT:
|
|
|
|
return (int64_t)x < (int64_t)y;
|
|
|
|
case TCG_COND_GE:
|
|
|
|
return (int64_t)x >= (int64_t)y;
|
|
|
|
case TCG_COND_LE:
|
|
|
|
return (int64_t)x <= (int64_t)y;
|
|
|
|
case TCG_COND_GT:
|
|
|
|
return (int64_t)x > (int64_t)y;
|
|
|
|
case TCG_COND_LTU:
|
|
|
|
return x < y;
|
|
|
|
case TCG_COND_GEU:
|
|
|
|
return x >= y;
|
|
|
|
case TCG_COND_LEU:
|
|
|
|
return x <= y;
|
|
|
|
case TCG_COND_GTU:
|
|
|
|
return x > y;
|
|
|
|
default:
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool do_constant_folding_cond_eq(TCGCond c)
|
|
|
|
{
|
|
|
|
switch (c) {
|
|
|
|
case TCG_COND_GT:
|
|
|
|
case TCG_COND_LTU:
|
|
|
|
case TCG_COND_LT:
|
|
|
|
case TCG_COND_GTU:
|
|
|
|
case TCG_COND_NE:
|
|
|
|
return 0;
|
|
|
|
case TCG_COND_GE:
|
|
|
|
case TCG_COND_GEU:
|
|
|
|
case TCG_COND_LE:
|
|
|
|
case TCG_COND_LEU:
|
|
|
|
case TCG_COND_EQ:
|
|
|
|
return 1;
|
|
|
|
default:
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return 2 if the condition can't be simplified, and the result
|
|
|
|
of the condition (0 or 1) if it can */
|
|
|
|
static TCGArg do_constant_folding_cond(TCGContext *s, TCGOpcode op, TCGArg x,
|
|
|
|
TCGArg y, TCGCond c)
|
|
|
|
{
|
|
|
|
struct tcg_temp_info *temps = s->temps2;
|
|
|
|
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, x) && temp_is_const(s, y)) {
|
2015-08-21 07:04:50 +00:00
|
|
|
switch (op_bits(s, op)) {
|
|
|
|
case 32:
|
|
|
|
return do_constant_folding_cond_32(temps[x].val, temps[y].val, c);
|
|
|
|
case 64:
|
|
|
|
return do_constant_folding_cond_64(temps[x].val, temps[y].val, c);
|
|
|
|
default:
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
} else if (temps_are_copies(s, x, y)) {
|
|
|
|
return do_constant_folding_cond_eq(c);
|
2018-02-11 03:05:19 +00:00
|
|
|
} else if (temp_is_const(s, y) && temps[y].val == 0) {
|
2015-08-21 07:04:50 +00:00
|
|
|
switch (c) {
|
|
|
|
case TCG_COND_LTU:
|
|
|
|
return 0;
|
|
|
|
case TCG_COND_GEU:
|
|
|
|
return 1;
|
|
|
|
default:
|
|
|
|
return 2;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
return 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return 2 if the condition can't be simplified, and the result
|
|
|
|
of the condition (0 or 1) if it can */
|
|
|
|
static TCGArg do_constant_folding_cond2(TCGContext *s, TCGArg *p1, TCGArg *p2, TCGCond c)
|
|
|
|
{
|
|
|
|
struct tcg_temp_info *temps = s->temps2;
|
|
|
|
|
|
|
|
TCGArg al = p1[0], ah = p1[1];
|
|
|
|
TCGArg bl = p2[0], bh = p2[1];
|
|
|
|
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, bl) && temp_is_const(s, bh)) {
|
2015-08-21 07:04:50 +00:00
|
|
|
uint64_t b = ((uint64_t)temps[bh].val << 32) | (uint32_t)temps[bl].val;
|
|
|
|
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, al) && temp_is_const(s, ah)) {
|
2015-08-21 07:04:50 +00:00
|
|
|
uint64_t a;
|
|
|
|
a = ((uint64_t)temps[ah].val << 32) | (uint32_t)temps[al].val;
|
|
|
|
return do_constant_folding_cond_64(a, b, c);
|
|
|
|
}
|
|
|
|
if (b == 0) {
|
|
|
|
switch (c) {
|
|
|
|
case TCG_COND_LTU:
|
|
|
|
return 0;
|
|
|
|
case TCG_COND_GEU:
|
|
|
|
return 1;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (temps_are_copies(s, al, bl) && temps_are_copies(s, ah, bh)) {
|
|
|
|
return do_constant_folding_cond_eq(c);
|
|
|
|
}
|
|
|
|
return 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool swap_commutative(TCGContext *s, TCGArg dest, TCGArg *p1, TCGArg *p2)
|
|
|
|
{
|
|
|
|
TCGArg a1 = *p1, a2 = *p2;
|
|
|
|
int sum = 0;
|
|
|
|
|
2018-02-11 03:05:19 +00:00
|
|
|
sum += temp_is_const(s, a1);
|
|
|
|
sum -= temp_is_const(s, a2);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
/* Prefer the constant in second argument, and then the form
|
|
|
|
op a, a, b, which is better handled on non-RISC hosts. */
|
|
|
|
if (sum > 0 || (sum == 0 && dest == a2)) {
|
|
|
|
*p1 = a2;
|
|
|
|
*p2 = a1;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool swap_commutative2(TCGContext *s, TCGArg *p1, TCGArg *p2)
|
|
|
|
{
|
|
|
|
int sum = 0;
|
|
|
|
|
2018-02-11 03:05:19 +00:00
|
|
|
sum += temp_is_const(s, p1[0]);
|
|
|
|
sum += temp_is_const(s, p1[1]);
|
|
|
|
sum -= temp_is_const(s, p2[0]);
|
|
|
|
sum -= temp_is_const(s, p2[1]);
|
2015-08-21 07:04:50 +00:00
|
|
|
if (sum > 0) {
|
|
|
|
TCGArg t;
|
|
|
|
t = p1[0], p1[0] = p2[0], p2[0] = t;
|
|
|
|
t = p1[1], p1[1] = p2[1], p2[1] = t;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Propagate constants and copies, fold constant expressions. */
|
2018-02-11 02:36:11 +00:00
|
|
|
void tcg_optimize(TCGContext *s)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
|
|
|
struct tcg_temp_info *temps = s->temps2;
|
2018-02-09 14:54:01 +00:00
|
|
|
int oi, oi_next, nb_temps, nb_globals;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
/* Array VALS has an element for each temp.
|
|
|
|
If this temp holds a constant then its value is kept in VALS' element.
|
|
|
|
If this temp is a copy of other ones then the other copies are
|
|
|
|
available through the doubly linked circular list. */
|
|
|
|
|
|
|
|
nb_temps = s->nb_temps;
|
|
|
|
nb_globals = s->nb_globals;
|
|
|
|
reset_all_temps(s, nb_temps);
|
|
|
|
|
2018-02-09 14:54:01 +00:00
|
|
|
for (oi = s->gen_first_op_idx; oi >= 0; oi = oi_next) {
|
2015-08-21 07:04:50 +00:00
|
|
|
tcg_target_ulong mask, partmask, affected;
|
2018-02-09 14:54:01 +00:00
|
|
|
int nb_oargs, nb_iargs, i;
|
2015-08-21 07:04:50 +00:00
|
|
|
TCGArg tmp;
|
|
|
|
|
2018-02-09 14:54:01 +00:00
|
|
|
TCGOp * const op = &s->gen_op_buf[oi];
|
|
|
|
TCGArg * const args = &s->gen_opparam_buf[op->args];
|
|
|
|
TCGOpcode opc = op->opc;
|
|
|
|
const TCGOpDef *def = &s->tcg_op_defs[opc];
|
|
|
|
|
|
|
|
oi_next = op->next;
|
2018-02-11 02:46:58 +00:00
|
|
|
|
|
|
|
/* Count the arguments, and initialize the temps that are
|
|
|
|
going to be used */
|
2018-02-09 14:54:01 +00:00
|
|
|
if (opc == INDEX_op_call) {
|
|
|
|
nb_oargs = op->callo;
|
|
|
|
nb_iargs = op->calli;
|
2018-02-11 02:46:58 +00:00
|
|
|
for (i = 0; i < nb_oargs + nb_iargs; i++) {
|
|
|
|
tmp = args[i];
|
|
|
|
if (tmp != TCG_CALL_DUMMY_ARG) {
|
|
|
|
init_temp_info(s, tmp);
|
|
|
|
}
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
nb_oargs = def->nb_oargs;
|
|
|
|
nb_iargs = def->nb_iargs;
|
2018-02-11 02:46:58 +00:00
|
|
|
for (i = 0; i < nb_oargs + nb_iargs; i++) {
|
|
|
|
init_temp_info(s, args[i]);
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Do copy propagation */
|
|
|
|
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_copy(s, args[i])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
args[i] = find_better_copy(s, args[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For commutative operations make constant second argument */
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(add):
|
|
|
|
CASE_OP_32_64(mul):
|
|
|
|
CASE_OP_32_64(and):
|
|
|
|
CASE_OP_32_64(or):
|
|
|
|
CASE_OP_32_64(xor):
|
|
|
|
CASE_OP_32_64(eqv):
|
|
|
|
CASE_OP_32_64(nand):
|
|
|
|
CASE_OP_32_64(nor):
|
|
|
|
CASE_OP_32_64(muluh):
|
|
|
|
CASE_OP_32_64(mulsh):
|
|
|
|
swap_commutative(s, args[0], &args[1], &args[2]);
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(brcond):
|
|
|
|
if (swap_commutative(s, -1, &args[0], &args[1])) {
|
|
|
|
args[2] = tcg_swap_cond(args[2]);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(setcond):
|
|
|
|
if (swap_commutative(s, args[0], &args[1], &args[2])) {
|
|
|
|
args[3] = tcg_swap_cond(args[3]);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(movcond):
|
|
|
|
if (swap_commutative(s, -1, &args[1], &args[2])) {
|
|
|
|
args[5] = tcg_swap_cond(args[5]);
|
|
|
|
}
|
|
|
|
/* For movcond, we canonicalize the "false" input reg to match
|
|
|
|
the destination reg so that the tcg backend can implement
|
|
|
|
a "move if true" operation. */
|
|
|
|
if (swap_commutative(s, args[0], &args[4], &args[3])) {
|
|
|
|
args[5] = tcg_invert_cond(args[5]);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(add2):
|
|
|
|
swap_commutative(s, args[0], &args[2], &args[4]);
|
|
|
|
swap_commutative(s, args[1], &args[3], &args[5]);
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(mulu2):
|
|
|
|
CASE_OP_32_64(muls2):
|
|
|
|
swap_commutative(s, args[0], &args[2], &args[3]);
|
|
|
|
break;
|
|
|
|
case INDEX_op_brcond2_i32:
|
|
|
|
if (swap_commutative2(s, &args[0], &args[2])) {
|
|
|
|
args[4] = tcg_swap_cond(args[4]);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case INDEX_op_setcond2_i32:
|
|
|
|
if (swap_commutative2(s, &args[1], &args[3])) {
|
|
|
|
args[5] = tcg_swap_cond(args[5]);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Simplify expressions for "shift/rot r, 0, a => movi r, 0",
|
|
|
|
and "sub r, 0, a => neg r, a" case. */
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(shl):
|
|
|
|
CASE_OP_32_64(shr):
|
|
|
|
CASE_OP_32_64(sar):
|
|
|
|
CASE_OP_32_64(rotl):
|
|
|
|
CASE_OP_32_64(rotr):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[1]) && temps[args[1]].val == 0) {
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], 0);
|
2015-08-21 07:04:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(sub):
|
|
|
|
{
|
|
|
|
TCGOpcode neg_op;
|
|
|
|
bool have_neg;
|
|
|
|
|
2018-02-11 03:11:15 +00:00
|
|
|
if (temp_is_const(s, args[2])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Proceed with possible constant folding. */
|
|
|
|
break;
|
|
|
|
}
|
2018-02-09 14:54:01 +00:00
|
|
|
if (opc == INDEX_op_sub_i32) {
|
2015-08-21 07:04:50 +00:00
|
|
|
neg_op = INDEX_op_neg_i32;
|
|
|
|
have_neg = TCG_TARGET_HAS_neg_i32;
|
|
|
|
} else {
|
|
|
|
neg_op = INDEX_op_neg_i64;
|
|
|
|
have_neg = TCG_TARGET_HAS_neg_i64;
|
|
|
|
}
|
|
|
|
if (!have_neg) {
|
|
|
|
break;
|
|
|
|
}
|
2018-02-11 03:11:15 +00:00
|
|
|
if (temp_is_const(s, args[1]) && temps[args[1]].val == 0) {
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = neg_op;
|
2015-08-21 07:04:50 +00:00
|
|
|
reset_temp(s, args[0]);
|
2018-02-09 14:54:01 +00:00
|
|
|
args[1] = args[2];
|
2015-08-21 07:04:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(xor):
|
|
|
|
CASE_OP_32_64(nand):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (!temp_is_const(s, args[1])
|
|
|
|
&& temp_is_const(s, args[2]) && temps[args[2]].val == -1) {
|
2015-08-21 07:04:50 +00:00
|
|
|
i = 1;
|
|
|
|
goto try_not;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(nor):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (!temp_is_const(s, args[1])
|
|
|
|
&& temp_is_const(s, args[2]) && temps[args[2]].val == 0) {
|
2015-08-21 07:04:50 +00:00
|
|
|
i = 1;
|
|
|
|
goto try_not;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(andc):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (!temp_is_const(s, args[2])
|
|
|
|
&& temp_is_const(s, args[1]) && temps[args[1]].val == -1) {
|
2015-08-21 07:04:50 +00:00
|
|
|
i = 2;
|
|
|
|
goto try_not;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(orc):
|
|
|
|
CASE_OP_32_64(eqv):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (!temp_is_const(s, args[2])
|
|
|
|
&& temp_is_const(s, args[1]) && temps[args[1]].val == 0) {
|
2015-08-21 07:04:50 +00:00
|
|
|
i = 2;
|
|
|
|
goto try_not;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
try_not:
|
|
|
|
{
|
|
|
|
TCGOpcode not_op;
|
|
|
|
bool have_not;
|
|
|
|
|
|
|
|
if (def->flags & TCG_OPF_64BIT) {
|
|
|
|
not_op = INDEX_op_not_i64;
|
|
|
|
have_not = TCG_TARGET_HAS_not_i64;
|
|
|
|
} else {
|
|
|
|
not_op = INDEX_op_not_i32;
|
|
|
|
have_not = TCG_TARGET_HAS_not_i32;
|
|
|
|
}
|
|
|
|
if (!have_not) {
|
|
|
|
break;
|
|
|
|
}
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = not_op;
|
2015-08-21 07:04:50 +00:00
|
|
|
reset_temp(s, args[0]);
|
2018-02-09 14:54:01 +00:00
|
|
|
args[1] = args[i];
|
2015-08-21 07:04:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Simplify expression for "op r, a, const => mov r, a" cases */
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(add):
|
|
|
|
CASE_OP_32_64(sub):
|
|
|
|
CASE_OP_32_64(shl):
|
|
|
|
CASE_OP_32_64(shr):
|
|
|
|
CASE_OP_32_64(sar):
|
|
|
|
CASE_OP_32_64(rotl):
|
|
|
|
CASE_OP_32_64(rotr):
|
|
|
|
CASE_OP_32_64(or):
|
|
|
|
CASE_OP_32_64(xor):
|
|
|
|
CASE_OP_32_64(andc):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (!temp_is_const(s, args[1])
|
|
|
|
&& temp_is_const(s, args[2]) && temps[args[2]].val == 0) {
|
2018-02-11 02:33:39 +00:00
|
|
|
tcg_opt_gen_mov(s, op, args, args[0], args[1]);
|
|
|
|
continue;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(and):
|
|
|
|
CASE_OP_32_64(orc):
|
|
|
|
CASE_OP_32_64(eqv):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (!temp_is_const(s, args[1])
|
|
|
|
&& temp_is_const(s, args[2]) && temps[args[2]].val == -1) {
|
2018-02-11 02:33:39 +00:00
|
|
|
tcg_opt_gen_mov(s, op, args, args[0], args[1]);
|
|
|
|
continue;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Simplify using known-zero bits. Currently only ops with a single
|
|
|
|
output argument is supported. */
|
|
|
|
mask = -1;
|
|
|
|
affected = -1;
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(ext8s):
|
|
|
|
if ((temps[args[1]].mask & 0x80) != 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
CASE_OP_32_64(ext8u):
|
|
|
|
mask = 0xff;
|
|
|
|
goto and_const;
|
|
|
|
CASE_OP_32_64(ext16s):
|
|
|
|
if ((temps[args[1]].mask & 0x8000) != 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
CASE_OP_32_64(ext16u):
|
|
|
|
mask = 0xffff;
|
|
|
|
goto and_const;
|
|
|
|
case INDEX_op_ext32s_i64:
|
|
|
|
if ((temps[args[1]].mask & 0x80000000) != 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case INDEX_op_ext32u_i64:
|
|
|
|
mask = 0xffffffffU;
|
|
|
|
goto and_const;
|
|
|
|
|
|
|
|
CASE_OP_32_64(and):
|
|
|
|
mask = temps[args[2]].mask;
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
and_const:
|
|
|
|
affected = temps[args[1]].mask & ~mask;
|
|
|
|
}
|
|
|
|
mask = temps[args[1]].mask & mask;
|
|
|
|
break;
|
|
|
|
|
2018-02-11 03:47:05 +00:00
|
|
|
case INDEX_op_ext_i32_i64:
|
|
|
|
if ((temps[args[1]].mask & 0x80000000) != 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case INDEX_op_extu_i32_i64:
|
|
|
|
/* We do not compute affected as it is a size changing op. */
|
|
|
|
mask = (uint32_t)temps[args[1]].mask;
|
|
|
|
break;
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(andc):
|
|
|
|
/* Known-zeros does not imply known-ones. Therefore unless
|
|
|
|
args[2] is constant, we can't infer anything from it. */
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
mask = ~temps[args[2]].mask;
|
|
|
|
goto and_const;
|
|
|
|
}
|
|
|
|
/* But we certainly know nothing outside args[1] may be set. */
|
|
|
|
mask = temps[args[1]].mask;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case INDEX_op_sar_i32:
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
tmp = temps[args[2]].val & 31;
|
|
|
|
mask = (int32_t)temps[args[1]].mask >> tmp;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case INDEX_op_sar_i64:
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
tmp = temps[args[2]].val & 63;
|
|
|
|
mask = (int64_t)temps[args[1]].mask >> tmp;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case INDEX_op_shr_i32:
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
tmp = temps[args[2]].val & 31;
|
|
|
|
mask = (uint32_t)temps[args[1]].mask >> tmp;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case INDEX_op_shr_i64:
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
tmp = temps[args[2]].val & 63;
|
|
|
|
mask = (uint64_t)temps[args[1]].mask >> tmp;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2018-02-11 03:24:03 +00:00
|
|
|
case INDEX_op_trunc_shr_i64_i32:
|
2015-08-21 07:04:50 +00:00
|
|
|
mask = (uint64_t)temps[args[1]].mask >> args[2];
|
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(shl):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
tmp = temps[args[2]].val & (TCG_TARGET_REG_BITS - 1);
|
|
|
|
mask = temps[args[1]].mask << tmp;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(neg):
|
|
|
|
/* Set to 1 all bits to the left of the rightmost. */
|
2017-01-19 11:50:28 +00:00
|
|
|
mask = 0-(temps[args[1]].mask & (0-temps[args[1]].mask));
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(deposit):
|
2017-01-19 11:50:28 +00:00
|
|
|
mask = (tcg_target_ulong)deposit64(temps[args[1]].mask, args[3], args[4],
|
2015-08-21 07:04:50 +00:00
|
|
|
temps[args[2]].mask);
|
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(or):
|
|
|
|
CASE_OP_32_64(xor):
|
|
|
|
mask = temps[args[1]].mask | temps[args[2]].mask;
|
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(setcond):
|
|
|
|
case INDEX_op_setcond2_i32:
|
|
|
|
mask = 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(movcond):
|
|
|
|
mask = temps[args[3]].mask | temps[args[4]].mask;
|
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(ld8u):
|
|
|
|
mask = 0xff;
|
|
|
|
break;
|
|
|
|
CASE_OP_32_64(ld16u):
|
|
|
|
mask = 0xffff;
|
|
|
|
break;
|
|
|
|
case INDEX_op_ld32u_i64:
|
|
|
|
mask = 0xffffffffu;
|
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(qemu_ld):
|
|
|
|
{
|
2018-02-11 00:01:17 +00:00
|
|
|
TCGMemOpIdx oi = args[nb_oargs + nb_iargs];
|
|
|
|
TCGMemOp mop = get_memop(oi);
|
2015-08-21 07:04:50 +00:00
|
|
|
if (!(mop & MO_SIGN)) {
|
|
|
|
mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 32-bit ops generate 32-bit results. For the result is zero test
|
|
|
|
below, we can ignore high bits, but for further optimizations we
|
|
|
|
need to record that the high bits contain garbage. */
|
|
|
|
partmask = mask;
|
|
|
|
if (!(def->flags & TCG_OPF_64BIT)) {
|
|
|
|
mask |= ~(tcg_target_ulong)0xffffffffu;
|
|
|
|
partmask &= 0xffffffffu;
|
|
|
|
affected &= 0xffffffffu;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (partmask == 0) {
|
|
|
|
assert(nb_oargs == 1);
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], 0);
|
2015-08-21 07:04:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (affected == 0) {
|
|
|
|
assert(nb_oargs == 1);
|
2018-02-11 02:33:39 +00:00
|
|
|
tcg_opt_gen_mov(s, op, args, args[0], args[1]);
|
2015-08-21 07:04:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Simplify expression for "op r, a, 0 => movi r, 0" cases */
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(and):
|
|
|
|
CASE_OP_32_64(mul):
|
|
|
|
CASE_OP_32_64(muluh):
|
|
|
|
CASE_OP_32_64(mulsh):
|
2018-02-11 03:05:19 +00:00
|
|
|
if ((temp_is_const(s, args[2]) && temps[args[2]].val == 0)) {
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], 0);
|
2015-08-21 07:04:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Simplify expression for "op r, a, a => mov r, a" cases */
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(or):
|
|
|
|
CASE_OP_32_64(and):
|
|
|
|
if (temps_are_copies(s, args[1], args[2])) {
|
2018-02-11 02:33:39 +00:00
|
|
|
tcg_opt_gen_mov(s, op, args, args[0], args[1]);
|
2015-08-21 07:04:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Simplify expression for "op r, a, a => movi r, 0" cases */
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(andc):
|
|
|
|
CASE_OP_32_64(sub):
|
|
|
|
CASE_OP_32_64(xor):
|
|
|
|
if (temps_are_copies(s, args[1], args[2])) {
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], 0);
|
2015-08-21 07:04:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Propagate constants through copy operations and do constant
|
|
|
|
folding. Constants will be substituted to arguments by register
|
|
|
|
allocator where needed and possible. Also detect copies. */
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(mov):
|
2018-02-11 02:33:39 +00:00
|
|
|
tcg_opt_gen_mov(s, op, args, args[0], args[1]);
|
|
|
|
break;
|
2015-08-21 07:04:50 +00:00
|
|
|
CASE_OP_32_64(movi):
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], args[1]);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
CASE_OP_32_64(not):
|
|
|
|
CASE_OP_32_64(neg):
|
|
|
|
CASE_OP_32_64(ext8s):
|
|
|
|
CASE_OP_32_64(ext8u):
|
|
|
|
CASE_OP_32_64(ext16s):
|
|
|
|
CASE_OP_32_64(ext16u):
|
|
|
|
case INDEX_op_ext32s_i64:
|
|
|
|
case INDEX_op_ext32u_i64:
|
2018-02-11 03:47:05 +00:00
|
|
|
case INDEX_op_ext_i32_i64:
|
|
|
|
case INDEX_op_extu_i32_i64:
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[1])) {
|
2018-02-09 14:54:01 +00:00
|
|
|
tmp = do_constant_folding(s, opc, temps[args[1]].val, 0);
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], tmp);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
2018-02-11 03:24:03 +00:00
|
|
|
case INDEX_op_trunc_shr_i64_i32:
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[1])) {
|
2018-02-09 14:54:01 +00:00
|
|
|
tmp = do_constant_folding(s, opc, temps[args[1]].val, args[2]);
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], tmp);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
|
|
|
CASE_OP_32_64(add):
|
|
|
|
CASE_OP_32_64(sub):
|
|
|
|
CASE_OP_32_64(mul):
|
|
|
|
CASE_OP_32_64(or):
|
|
|
|
CASE_OP_32_64(and):
|
|
|
|
CASE_OP_32_64(xor):
|
|
|
|
CASE_OP_32_64(shl):
|
|
|
|
CASE_OP_32_64(shr):
|
|
|
|
CASE_OP_32_64(sar):
|
|
|
|
CASE_OP_32_64(rotl):
|
|
|
|
CASE_OP_32_64(rotr):
|
|
|
|
CASE_OP_32_64(andc):
|
|
|
|
CASE_OP_32_64(orc):
|
|
|
|
CASE_OP_32_64(eqv):
|
|
|
|
CASE_OP_32_64(nand):
|
|
|
|
CASE_OP_32_64(nor):
|
|
|
|
CASE_OP_32_64(muluh):
|
|
|
|
CASE_OP_32_64(mulsh):
|
|
|
|
CASE_OP_32_64(div):
|
|
|
|
CASE_OP_32_64(divu):
|
|
|
|
CASE_OP_32_64(rem):
|
|
|
|
CASE_OP_32_64(remu):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[1]) && temp_is_const(s, args[2])) {
|
2018-02-09 14:54:01 +00:00
|
|
|
tmp = do_constant_folding(s, opc, temps[args[1]].val,
|
2015-08-21 07:04:50 +00:00
|
|
|
temps[args[2]].val);
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], tmp);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
|
|
|
CASE_OP_32_64(deposit):
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[1]) && temp_is_const(s, args[2])) {
|
2017-01-19 11:50:28 +00:00
|
|
|
tmp = (TCGArg)deposit64(temps[args[1]].val, args[3], args[4],
|
2015-08-21 07:04:50 +00:00
|
|
|
temps[args[2]].val);
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], tmp);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
|
|
|
CASE_OP_32_64(setcond):
|
2018-02-09 14:54:01 +00:00
|
|
|
tmp = do_constant_folding_cond(s, opc, args[1], args[2], args[3]);
|
2015-08-21 07:04:50 +00:00
|
|
|
if (tmp != 2) {
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], tmp);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
|
|
|
CASE_OP_32_64(brcond):
|
2018-02-09 14:54:01 +00:00
|
|
|
tmp = do_constant_folding_cond(s, opc, args[0], args[1], args[2]);
|
2015-08-21 07:04:50 +00:00
|
|
|
if (tmp != 2) {
|
|
|
|
if (tmp) {
|
|
|
|
reset_all_temps(s, nb_temps);
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = INDEX_op_br;
|
|
|
|
args[0] = args[3];
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
2018-02-09 18:03:25 +00:00
|
|
|
tcg_op_remove(s, op);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
|
|
|
CASE_OP_32_64(movcond):
|
2018-02-09 14:54:01 +00:00
|
|
|
tmp = do_constant_folding_cond(s, opc, args[1], args[2], args[5]);
|
2015-08-21 07:04:50 +00:00
|
|
|
if (tmp != 2) {
|
2018-02-11 02:33:39 +00:00
|
|
|
tcg_opt_gen_mov(s, op, args, args[0], args[4-tmp]);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
|
|
|
case INDEX_op_add2_i32:
|
|
|
|
case INDEX_op_sub2_i32:
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2]) && temp_is_const(s, args[3])
|
|
|
|
&& temp_is_const(s, args[4]) && temp_is_const(s, args[5])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
uint32_t al = temps[args[2]].val;
|
|
|
|
uint32_t ah = temps[args[3]].val;
|
|
|
|
uint32_t bl = temps[args[4]].val;
|
|
|
|
uint32_t bh = temps[args[5]].val;
|
|
|
|
uint64_t a = ((uint64_t)ah << 32) | al;
|
|
|
|
uint64_t b = ((uint64_t)bh << 32) | bl;
|
|
|
|
TCGArg rl, rh;
|
2018-02-09 18:11:19 +00:00
|
|
|
TCGOp *op2 = insert_op_before(s, op, INDEX_op_movi_i32, 2);
|
|
|
|
TCGArg *args2 = &s->gen_opparam_buf[op2->args];
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-09 14:54:01 +00:00
|
|
|
if (opc == INDEX_op_add2_i32) {
|
2015-08-21 07:04:50 +00:00
|
|
|
a += b;
|
|
|
|
} else {
|
|
|
|
a -= b;
|
|
|
|
}
|
|
|
|
|
|
|
|
rl = args[0];
|
|
|
|
rh = args[1];
|
tcg/optimize: fix constant signedness
By convention, on a 64-bit host TCG internally stores 32-bit constants
as sign-extended. This is not the case in the optimizer when a 32-bit
constant is folded.
This doesn't seem to have more consequences than suboptimal code
generation. For instance the x86 backend assumes sign-extended constants,
and in some rare cases uses a 32-bit unsigned immediate 0xffffffff
instead of a 8-bit signed immediate 0xff for the constant -1. This is
with a ppc guest:
before
------
---- 0x9f29cc
movi_i32 tmp1,$0xffffffff
movi_i32 tmp2,$0x0
add2_i32 tmp0,CA,CA,tmp2,r6,tmp2
add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2
mov_i32 r10,tmp0
0x7fd8c7dfe90c: xor %ebp,%ebp
0x7fd8c7dfe90e: mov %ebp,%r11d
0x7fd8c7dfe911: mov 0x18(%r14),%r9d
0x7fd8c7dfe915: add %r9d,%r10d
0x7fd8c7dfe918: adc %ebp,%r11d
0x7fd8c7dfe91b: add $0xffffffff,%r10d
0x7fd8c7dfe922: adc %ebp,%r11d
0x7fd8c7dfe925: mov %r11d,0x134(%r14)
0x7fd8c7dfe92c: mov %r10d,0x28(%r14)
after
-----
---- 0x9f29cc
movi_i32 tmp1,$0xffffffffffffffff
movi_i32 tmp2,$0x0
add2_i32 tmp0,CA,CA,tmp2,r6,tmp2
add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2
mov_i32 r10,tmp0
0x7f37010d490c: xor %ebp,%ebp
0x7f37010d490e: mov %ebp,%r11d
0x7f37010d4911: mov 0x18(%r14),%r9d
0x7f37010d4915: add %r9d,%r10d
0x7f37010d4918: adc %ebp,%r11d
0x7f37010d491b: add $0xffffffffffffffff,%r10d
0x7f37010d491f: adc %ebp,%r11d
0x7f37010d4922: mov %r11d,0x134(%r14)
0x7f37010d4929: mov %r10d,0x28(%r14)
Backports commit 29f3ff8d6cbc28f79933aeaa25805408d0984a8f from qemu
2018-02-11 02:39:52 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, rl, (int32_t)a);
|
|
|
|
tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(a >> 32));
|
2018-02-09 14:54:01 +00:00
|
|
|
|
|
|
|
/* We've done all we need to do with the movi. Skip it. */
|
|
|
|
oi_next = op2->next;
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
|
|
|
case INDEX_op_mulu2_i32:
|
2018-02-11 03:05:19 +00:00
|
|
|
if (temp_is_const(s, args[2]) && temp_is_const(s, args[3])) {
|
2015-08-21 07:04:50 +00:00
|
|
|
uint32_t a = temps[args[2]].val;
|
|
|
|
uint32_t b = temps[args[3]].val;
|
|
|
|
uint64_t r = (uint64_t)a * b;
|
|
|
|
TCGArg rl, rh;
|
2018-02-09 18:11:19 +00:00
|
|
|
TCGOp *op2 = insert_op_before(s, op, INDEX_op_movi_i32, 2);
|
|
|
|
TCGArg *args2 = &s->gen_opparam_buf[op2->args];
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
rl = args[0];
|
|
|
|
rh = args[1];
|
tcg/optimize: fix constant signedness
By convention, on a 64-bit host TCG internally stores 32-bit constants
as sign-extended. This is not the case in the optimizer when a 32-bit
constant is folded.
This doesn't seem to have more consequences than suboptimal code
generation. For instance the x86 backend assumes sign-extended constants,
and in some rare cases uses a 32-bit unsigned immediate 0xffffffff
instead of a 8-bit signed immediate 0xff for the constant -1. This is
with a ppc guest:
before
------
---- 0x9f29cc
movi_i32 tmp1,$0xffffffff
movi_i32 tmp2,$0x0
add2_i32 tmp0,CA,CA,tmp2,r6,tmp2
add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2
mov_i32 r10,tmp0
0x7fd8c7dfe90c: xor %ebp,%ebp
0x7fd8c7dfe90e: mov %ebp,%r11d
0x7fd8c7dfe911: mov 0x18(%r14),%r9d
0x7fd8c7dfe915: add %r9d,%r10d
0x7fd8c7dfe918: adc %ebp,%r11d
0x7fd8c7dfe91b: add $0xffffffff,%r10d
0x7fd8c7dfe922: adc %ebp,%r11d
0x7fd8c7dfe925: mov %r11d,0x134(%r14)
0x7fd8c7dfe92c: mov %r10d,0x28(%r14)
after
-----
---- 0x9f29cc
movi_i32 tmp1,$0xffffffffffffffff
movi_i32 tmp2,$0x0
add2_i32 tmp0,CA,CA,tmp2,r6,tmp2
add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2
mov_i32 r10,tmp0
0x7f37010d490c: xor %ebp,%ebp
0x7f37010d490e: mov %ebp,%r11d
0x7f37010d4911: mov 0x18(%r14),%r9d
0x7f37010d4915: add %r9d,%r10d
0x7f37010d4918: adc %ebp,%r11d
0x7f37010d491b: add $0xffffffffffffffff,%r10d
0x7f37010d491f: adc %ebp,%r11d
0x7f37010d4922: mov %r11d,0x134(%r14)
0x7f37010d4929: mov %r10d,0x28(%r14)
Backports commit 29f3ff8d6cbc28f79933aeaa25805408d0984a8f from qemu
2018-02-11 02:39:52 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, rl, (int32_t)r);
|
|
|
|
tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(r >> 32));
|
2018-02-09 14:54:01 +00:00
|
|
|
|
|
|
|
/* We've done all we need to do with the movi. Skip it. */
|
|
|
|
oi_next = op2->next;
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
|
|
|
|
case INDEX_op_brcond2_i32:
|
|
|
|
tmp = do_constant_folding_cond2(s, &args[0], &args[2], args[4]);
|
|
|
|
if (tmp != 2) {
|
|
|
|
if (tmp) {
|
|
|
|
do_brcond_true:
|
|
|
|
reset_all_temps(s, nb_temps);
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = INDEX_op_br;
|
|
|
|
args[0] = args[5];
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
do_brcond_false:
|
2018-02-09 18:03:25 +00:00
|
|
|
tcg_op_remove(s, op);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
} else if ((args[4] == TCG_COND_LT || args[4] == TCG_COND_GE)
|
2018-02-11 03:05:19 +00:00
|
|
|
&& temp_is_const(s, args[2]) && temps[args[2]].val == 0
|
|
|
|
&& temp_is_const(s, args[3]) && temps[args[3]].val == 0) {
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Simplify LT/GE comparisons vs zero to a single compare
|
|
|
|
vs the high word of the input. */
|
|
|
|
do_brcond_high:
|
|
|
|
reset_all_temps(s, nb_temps);
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = INDEX_op_brcond_i32;
|
|
|
|
args[0] = args[1];
|
|
|
|
args[1] = args[3];
|
|
|
|
args[2] = args[4];
|
|
|
|
args[3] = args[5];
|
2015-08-21 07:04:50 +00:00
|
|
|
} else if (args[4] == TCG_COND_EQ) {
|
|
|
|
/* Simplify EQ comparisons where one of the pairs
|
|
|
|
can be simplified. */
|
|
|
|
tmp = do_constant_folding_cond(s, INDEX_op_brcond_i32,
|
|
|
|
args[0], args[2], TCG_COND_EQ);
|
|
|
|
if (tmp == 0) {
|
|
|
|
goto do_brcond_false;
|
|
|
|
} else if (tmp == 1) {
|
|
|
|
goto do_brcond_high;
|
|
|
|
}
|
|
|
|
tmp = do_constant_folding_cond(s, INDEX_op_brcond_i32,
|
|
|
|
args[1], args[3], TCG_COND_EQ);
|
|
|
|
if (tmp == 0) {
|
|
|
|
goto do_brcond_false;
|
|
|
|
} else if (tmp != 1) {
|
|
|
|
goto do_default;
|
|
|
|
}
|
|
|
|
do_brcond_low:
|
|
|
|
reset_all_temps(s, nb_temps);
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = INDEX_op_brcond_i32;
|
|
|
|
args[1] = args[2];
|
|
|
|
args[2] = args[4];
|
|
|
|
args[3] = args[5];
|
2015-08-21 07:04:50 +00:00
|
|
|
} else if (args[4] == TCG_COND_NE) {
|
|
|
|
/* Simplify NE comparisons where one of the pairs
|
|
|
|
can be simplified. */
|
|
|
|
tmp = do_constant_folding_cond(s, INDEX_op_brcond_i32,
|
|
|
|
args[0], args[2], TCG_COND_NE);
|
|
|
|
if (tmp == 0) {
|
|
|
|
goto do_brcond_high;
|
|
|
|
} else if (tmp == 1) {
|
|
|
|
goto do_brcond_true;
|
|
|
|
}
|
|
|
|
tmp = do_constant_folding_cond(s, INDEX_op_brcond_i32,
|
|
|
|
args[1], args[3], TCG_COND_NE);
|
|
|
|
if (tmp == 0) {
|
|
|
|
goto do_brcond_low;
|
|
|
|
} else if (tmp == 1) {
|
|
|
|
goto do_brcond_true;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
} else {
|
|
|
|
goto do_default;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case INDEX_op_setcond2_i32:
|
|
|
|
tmp = do_constant_folding_cond2(s, &args[1], &args[3], args[5]);
|
|
|
|
if (tmp != 2) {
|
|
|
|
do_setcond_const:
|
2018-02-11 02:20:34 +00:00
|
|
|
tcg_opt_gen_movi(s, op, args, args[0], tmp);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else if ((args[5] == TCG_COND_LT || args[5] == TCG_COND_GE)
|
2018-02-11 03:05:19 +00:00
|
|
|
&& temp_is_const(s, args[3]) && temps[args[3]].val == 0
|
|
|
|
&& temp_is_const(s, args[4]) && temps[args[4]].val == 0) {
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Simplify LT/GE comparisons vs zero to a single compare
|
|
|
|
vs the high word of the input. */
|
|
|
|
do_setcond_high:
|
|
|
|
reset_temp(s, args[0]);
|
|
|
|
temps[args[0]].mask = 1;
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = INDEX_op_setcond_i32;
|
|
|
|
args[1] = args[2];
|
|
|
|
args[2] = args[4];
|
|
|
|
args[3] = args[5];
|
2015-08-21 07:04:50 +00:00
|
|
|
} else if (args[5] == TCG_COND_EQ) {
|
|
|
|
/* Simplify EQ comparisons where one of the pairs
|
|
|
|
can be simplified. */
|
|
|
|
tmp = do_constant_folding_cond(s, INDEX_op_setcond_i32,
|
|
|
|
args[1], args[3], TCG_COND_EQ);
|
|
|
|
if (tmp == 0) {
|
|
|
|
goto do_setcond_const;
|
|
|
|
} else if (tmp == 1) {
|
|
|
|
goto do_setcond_high;
|
|
|
|
}
|
|
|
|
tmp = do_constant_folding_cond(s, INDEX_op_setcond_i32,
|
|
|
|
args[2], args[4], TCG_COND_EQ);
|
|
|
|
if (tmp == 0) {
|
|
|
|
goto do_setcond_high;
|
|
|
|
} else if (tmp != 1) {
|
|
|
|
goto do_default;
|
|
|
|
}
|
|
|
|
do_setcond_low:
|
|
|
|
reset_temp(s, args[0]);
|
|
|
|
temps[args[0]].mask = 1;
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = INDEX_op_setcond_i32;
|
|
|
|
args[2] = args[3];
|
|
|
|
args[3] = args[5];
|
2015-08-21 07:04:50 +00:00
|
|
|
} else if (args[5] == TCG_COND_NE) {
|
|
|
|
/* Simplify NE comparisons where one of the pairs
|
|
|
|
can be simplified. */
|
|
|
|
tmp = do_constant_folding_cond(s, INDEX_op_setcond_i32,
|
|
|
|
args[1], args[3], TCG_COND_NE);
|
|
|
|
if (tmp == 0) {
|
|
|
|
goto do_setcond_high;
|
|
|
|
} else if (tmp == 1) {
|
|
|
|
goto do_setcond_const;
|
|
|
|
}
|
|
|
|
tmp = do_constant_folding_cond(s, INDEX_op_setcond_i32,
|
|
|
|
args[2], args[4], TCG_COND_NE);
|
|
|
|
if (tmp == 0) {
|
|
|
|
goto do_setcond_low;
|
|
|
|
} else if (tmp == 1) {
|
|
|
|
goto do_setcond_const;
|
|
|
|
}
|
|
|
|
goto do_default;
|
|
|
|
} else {
|
|
|
|
goto do_default;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case INDEX_op_call:
|
|
|
|
if (!(args[nb_oargs + nb_iargs + 1]
|
|
|
|
& (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
|
|
|
|
for (i = 0; i < nb_globals; i++) {
|
2018-02-11 02:46:58 +00:00
|
|
|
if (test_bit(i, s->temps2_used.l)) {
|
|
|
|
reset_temp(s, i);
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
goto do_reset_output;
|
|
|
|
|
|
|
|
default:
|
|
|
|
do_default:
|
|
|
|
/* Default case: we know nothing about operation (or were unable
|
|
|
|
to compute the operation result) so no propagation is done.
|
|
|
|
We trash everything if the operation is the end of a basic
|
|
|
|
block, otherwise we only trash the output args. "mask" is
|
|
|
|
the non-zero bits mask for the first output arg. */
|
|
|
|
if (def->flags & TCG_OPF_BB_END) {
|
|
|
|
reset_all_temps(s, nb_temps);
|
|
|
|
} else {
|
|
|
|
do_reset_output:
|
|
|
|
for (i = 0; i < nb_oargs; i++) {
|
|
|
|
reset_temp(s, args[i]);
|
|
|
|
/* Save the corresponding known-zero bits mask for the
|
|
|
|
first output argument (only one supported so far). */
|
|
|
|
if (i == 0) {
|
|
|
|
temps[args[i]].mask = mask;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|