unicorn/qemu/tcg/i386/tcg-target.opc.h

/* Target-specific opcodes for host vector expansion.  These will be
   emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
   consider these to be UNSPEC with names.  */

DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC)
DEF(x86_vpblendvb_vec, 1, 3, 0, IMPLVEC)
DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)
DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)
DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)
DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)
tcg/i386: Add vector operations The x86 vector instruction set is extremely irregular. With newer editions, Intel has filled in some of the blanks. However, we don't get many 64-bit operations until SSE4.2, introduced in 2009. The subsequent edition was for AVX1, introduced in 2011, which added three-operand addressing, and adjusts how all instructions should be encoded. Given the relatively narrow 2 year window between possible to support and desirable to support, and to vastly simplify code maintainence, I am only planning to support AVX1 and later cpus. Backports commit 770c2fc7bb70804ae9869995fd02dadd6d7656ac from qemu 2018-03-06 21:20:28 +00:00			`/* Target-specific opcodes for host vector expansion. These will be`
			`emitted by tcg_expand_vec_op. For those familiar with GCC internals,`
			`consider these to be UNSPEC with names. */`

			`DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC)`
			`DEF(x86_vpblendvb_vec, 1, 3, 0, IMPLVEC)`
			`DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)`
			`DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)`
			`DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)`
			`DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)`
			`DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)`
			`DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)`
			`DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)`