unicorn/qemu/include/hw/riscv/spike.h

#ifndef HW_RISCV_SPIKE_H
#define HW_RISCV_SPIKE_H

void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc);

#endif /* HW_RISCV_SPIKE_H */
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality. 2019-03-08 18:06:28 +00:00			`#ifndef HW_RISCV_SPIKE_H`
			`#define HW_RISCV_SPIKE_H`

			`void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc);`

			`#endif /* HW_RISCV_SPIKE_H */`