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unicorn/qemu/target-arm/unicorn_aarch64.c

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import
2015-08-21 07:04:50 +00:00
/* Unicorn Emulator Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
#include "hw/boards.h"
#include "hw/arm/arm.h"
#include "sysemu/cpus.h"
#include "unicorn.h"
#include "cpu.h"
#include "unicorn_common.h"
move macros in `qemu/target-*/unicorn*.c` to `uc_priv.h`
2016-03-02 03:43:02 +00:00
#include "uc_priv.h"
import
2015-08-21 07:04:50 +00:00
New feature: registers can be bulk saved/restored in an opaque blob
2016-08-20 11:14:07 +00:00
const int ARM64_REGS_STORAGE_SIZE = offsetof(CPUARMState, tlb_table);
import
2015-08-21 07:04:50 +00:00
static void arm64_set_pc(struct uc_struct *uc, uint64_t address)
{
((CPUARMState *)uc->current_cpu->env_ptr)->pc = address;
}
Fix arm & arm64 memleaks
2016-01-31 22:22:20 +00:00
void arm64_release(void* ctx);
void arm64_release(void* ctx)
{
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
struct uc_struct* uc;
ARMCPU* cpu;
Fix arm & arm64 memleaks
2016-01-31 22:22:20 +00:00
TCGContext *s = (TCGContext *) ctx;
revert to use of g_free to make future qemu integrations easier (#695) * revert to use of g_free to make future qemu integrations easier * bracing
2016-12-21 14:28:36 +00:00
g_free(s->tb_ctx.tbs);
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
uc = s->uc;
cpu = (ARMCPU*) uc->cpu;
revert to use of g_free to make future qemu integrations easier (#695) * revert to use of g_free to make future qemu integrations easier * bracing
2016-12-21 14:28:36 +00:00
g_free(cpu->cpreg_indexes);
g_free(cpu->cpreg_values);
g_free(cpu->cpreg_vmstate_indexes);
g_free(cpu->cpreg_vmstate_values);
Fix arm & arm64 memleaks
2016-01-31 22:22:20 +00:00
release_common(ctx);
}
change uch to uc_struct (target-arm)
2015-08-26 10:30:58 +00:00
void arm64_reg_reset(struct uc_struct *uc)
import
2015-08-21 07:04:50 +00:00
{
remove uc->cpus
2016-09-23 14:38:21 +00:00
CPUArchState *env = uc->cpu->env_ptr;
import
2015-08-21 07:04:50 +00:00
memset(env->xregs, 0, sizeof(env->xregs));
env->pc = 0;
}
add batched reg access
2016-04-04 15:25:30 +00:00
int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
import
2015-08-21 07:04:50 +00:00
{
remove uc->cpus
2016-09-23 14:38:21 +00:00
CPUState *mycpu = uc->cpu;
add batched reg access
2016-04-04 15:25:30 +00:00
int i;
import
2015-08-21 07:04:50 +00:00
add batched reg access
2016-04-04 15:25:30 +00:00
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
void *value = vals[i];
uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774) * uc_reg_read & uc_reg_write now support ARM64 Neon registers * Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
2017-03-07 13:29:34 +00:00
// V & Q registers are the same
if (regid >= UC_ARM64_REG_V0 && regid <= UC_ARM64_REG_V31) {
regid += UC_ARM64_REG_Q0 - UC_ARM64_REG_V0;
}
reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) * reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 12:13:35 +00:00
if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) {
add batched reg access
2016-04-04 15:25:30 +00:00
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0];
reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) * reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 12:13:35 +00:00
} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
*(int32_t *)value = READ_DWORD(ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_W0]);
uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774) * uc_reg_read & uc_reg_write now support ARM64 Neon registers * Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
2017-03-07 13:29:34 +00:00
} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) {
float64 *dst = (float64*) value;
uint32_t reg_index = 2*(regid - UC_ARM64_REG_Q0);
dst[0] = ARM_CPU(uc, mycpu)->env.vfp.regs[reg_index];
dst[1] = ARM_CPU(uc, mycpu)->env.vfp.regs[reg_index+1];
} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
*(float64*)value = ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_D0)];
} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
*(int32_t*)value = READ_DWORD(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_S0)]);
} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
*(int16_t*)value = READ_WORD(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_H0)]);
} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
*(int8_t*)value = READ_BYTE_L(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_B0)]);
reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) * reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 12:13:35 +00:00
} else {
add batched reg access
2016-04-04 15:25:30 +00:00
switch(regid) {
default: break;
add arm64 CPACR_EL1 register support (#814)
2017-05-02 06:51:19 +00:00
case UC_ARM64_REG_CPACR_EL1:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc;
break;
aarch64: Add exception syndrome pseudo register.
2018-01-04 00:41:12 +00:00
case UC_ARM64_REG_ESR:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.exception.syndrome;
break;
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
case UC_ARM64_REG_TPIDR_EL0:
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[0];
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
break;
case UC_ARM64_REG_TPIDRRO_EL0:
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidrro_el[0];
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
break;
case UC_ARM64_REG_TPIDR_EL1:
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[1];
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
break;
add batched reg access
2016-04-04 15:25:30 +00:00
case UC_ARM64_REG_X29:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29];
break;
add batched reg access
2016-04-04 15:25:30 +00:00
case UC_ARM64_REG_X30:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[30];
break;
add batched reg access
2016-04-04 15:25:30 +00:00
case UC_ARM64_REG_PC:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
*(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc;
break;
add batched reg access
2016-04-04 15:25:30 +00:00
case UC_ARM64_REG_SP:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[31];
break;
unicorn_aarch64: Expose UC_ARM64_REG_NZCV register. (#791)
2017-03-31 02:21:45 +00:00
case UC_ARM64_REG_NZCV:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
break;
aarch64: Add pstate pseudoregister
2018-01-11 18:26:51 +00:00
case UC_ARM64_REG_PSTATE:
*(uint32_t *)value = pstate_read(&ARM_CPU(uc, mycpu)->env);
break;
aarch64: Add FPCR and FPSR registers
2018-01-11 18:28:59 +00:00
case UC_ARM64_REG_FPCR:
*(uint32_t *)value = vfp_get_fpcr(&ARM_CPU(uc, mycpu)->env);
break;
case UC_ARM64_REG_FPSR:
*(uint32_t *)value = vfp_get_fpsr(&ARM_CPU(uc, mycpu)->env);
break;
add batched reg access
2016-04-04 15:25:30 +00:00
}
import
2015-08-21 07:04:50 +00:00
}
}
return 0;
}
add batched reg access
2016-04-04 15:25:30 +00:00
int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
import
2015-08-21 07:04:50 +00:00
{
remove uc->cpus
2016-09-23 14:38:21 +00:00
CPUState *mycpu = uc->cpu;
add batched reg access
2016-04-04 15:25:30 +00:00
int i;
import
2015-08-21 07:04:50 +00:00
add batched reg access
2016-04-04 15:25:30 +00:00
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
const void *value = vals[i];
uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774) * uc_reg_read & uc_reg_write now support ARM64 Neon registers * Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
2017-03-07 13:29:34 +00:00
if (regid >= UC_ARM64_REG_V0 && regid <= UC_ARM64_REG_V31) {
regid += UC_ARM64_REG_Q0 - UC_ARM64_REG_V0;
}
reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) * reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 12:13:35 +00:00
if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) {
add batched reg access
2016-04-04 15:25:30 +00:00
ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(uint64_t *)value;
reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) * reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 12:13:35 +00:00
} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
WRITE_DWORD(ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value);
uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774) * uc_reg_read & uc_reg_write now support ARM64 Neon registers * Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
2017-03-07 13:29:34 +00:00
} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) {
float64 *src = (float64*) value;
uint32_t reg_index = 2*(regid - UC_ARM64_REG_Q0);
ARM_CPU(uc, mycpu)->env.vfp.regs[reg_index] = src[0];
ARM_CPU(uc, mycpu)->env.vfp.regs[reg_index+1] = src[1];
} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_D0)] = * (float64*) value;
} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
WRITE_DWORD(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_S0)], *(int32_t*) value);
} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
WRITE_WORD(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_H0)], *(int16_t*) value);
} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
WRITE_BYTE_L(ARM_CPU(uc, mycpu)->env.vfp.regs[2*(regid - UC_ARM64_REG_B0)], *(int8_t*) value);
reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) * reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 12:13:35 +00:00
} else {
add batched reg access
2016-04-04 15:25:30 +00:00
switch(regid) {
default: break;
add arm64 CPACR_EL1 register support (#814)
2017-05-02 06:51:19 +00:00
case UC_ARM64_REG_CPACR_EL1:
ARM_CPU(uc, mycpu)->env.cp15.c1_coproc = *(uint32_t *)value;
break;
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
case UC_ARM64_REG_TPIDR_EL0:
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[0] = *(uint64_t *)value;
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
break;
case UC_ARM64_REG_TPIDRRO_EL0:
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
ARM_CPU(uc, mycpu)->env.cp15.tpidrro_el[0] = *(uint64_t *)value;
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
break;
case UC_ARM64_REG_TPIDR_EL1:
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[1] = *(uint64_t *)value;
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
break;
add batched reg access
2016-04-04 15:25:30 +00:00
case UC_ARM64_REG_X29:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
ARM_CPU(uc, mycpu)->env.xregs[29] = *(uint64_t *)value;
break;
add batched reg access
2016-04-04 15:25:30 +00:00
case UC_ARM64_REG_X30:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
ARM_CPU(uc, mycpu)->env.xregs[30] = *(uint64_t *)value;
break;
add batched reg access
2016-04-04 15:25:30 +00:00
case UC_ARM64_REG_PC:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
// force to quit execution and flush TB
uc->quit_request = true;
uc_emu_stop(uc);
break;
add batched reg access
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case UC_ARM64_REG_SP:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
ARM_CPU(uc, mycpu)->env.xregs[31] = *(uint64_t *)value;
break;
unicorn_aarch64: Expose UC_ARM64_REG_NZCV register. (#791)
2017-03-31 02:21:45 +00:00
case UC_ARM64_REG_NZCV:
Aarch64 add thread registers (#834) * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 07:42:49 +00:00
cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV);
break;
aarch64: Add pstate pseudoregister
2018-01-11 18:26:51 +00:00
case UC_ARM64_REG_PSTATE:
pstate_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
break;
aarch64: Add FPCR and FPSR registers
2018-01-11 18:28:59 +00:00
case UC_ARM64_REG_FPCR:
vfp_set_fpcr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
break;
case UC_ARM64_REG_FPSR:
vfp_set_fpsr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
break;
add batched reg access
2016-04-04 15:25:30 +00:00
}
import
2015-08-21 07:04:50 +00:00
}
}
return 0;
}
This code should now build the x86_x64-softmmu part 2.
2017-01-19 11:50:28 +00:00
DEFAULT_VISIBILITY
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
#ifdef TARGET_WORDS_BIGENDIAN
void arm64eb_uc_init(struct uc_struct* uc)
#else
import
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void arm64_uc_init(struct uc_struct* uc)
arm64eb: add support for ARM64 big endian.
2017-04-24 15:25:30 +00:00
#endif
import
2015-08-21 07:04:50 +00:00
{
register_accel_types(uc);
arm_cpu_register_types(uc);
aarch64_cpu_register_types(uc);
machvirt_machine_init(uc);
uc->reg_read = arm64_reg_read;
uc->reg_write = arm64_reg_write;
uc->reg_reset = arm64_reg_reset;
uc->set_pc = arm64_set_pc;
Fix arm & arm64 memleaks
2016-01-31 22:22:20 +00:00
uc->release = arm64_release;
import
2015-08-21 07:04:50 +00:00
uc_common_init(uc);
}
Reference in a new issue Copy permalink