unicorn/qemu/target-mips/unicorn.c

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/* Unicorn Emulator Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
#include "hw/boards.h"
#include "hw/mips/mips.h"
#include "sysemu/cpus.h"
#include "unicorn.h"
#include "cpu.h"
#include "unicorn_common.h"
#include "uc_priv.h"
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#ifdef TARGET_MIPS64
const int MIPS64_REGS_STORAGE_SIZE = offsetof(CPUMIPSState, tlb_table);
#else // MIPS32
const int MIPS_REGS_STORAGE_SIZE = offsetof(CPUMIPSState, tlb_table);
#endif
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#ifdef TARGET_MIPS64
typedef uint64_t mipsreg_t;
#else
typedef uint32_t mipsreg_t;
#endif
static uint64_t mips_mem_redirect(uint64_t address)
{
// kseg0 range masks off high address bit
if (address >= 0x80000000 && address <= 0x9fffffff)
return address & 0x7fffffff;
// kseg1 range masks off top 3 address bits
if (address >= 0xa0000000 && address <= 0xbfffffff) {
return address & 0x1fffffff;
}
// no redirect
return address;
}
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static void mips_set_pc(struct uc_struct *uc, uint64_t address)
{
((CPUMIPSState *)uc->current_cpu->env_ptr)->active_tc.PC = address;
}
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void mips_release(void *ctx);
void mips_release(void *ctx)
{
MIPSCPU* cpu;
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int i;
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TCGContext *tcg_ctx = (TCGContext *) ctx;
release_common(ctx);
cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
g_free(cpu->env.tlb);
g_free(cpu->env.mvp);
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for (i = 0; i < 32; i++) {
g_free(tcg_ctx->cpu_gpr[i]);
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}
g_free(tcg_ctx->cpu_PC);
g_free(tcg_ctx->btarget);
g_free(tcg_ctx->bcond);
g_free(tcg_ctx->cpu_dspctrl);
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g_free(tcg_ctx->tb_ctx.tbs);
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}
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void mips_reg_reset(struct uc_struct *uc)
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{
CPUArchState *env;
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(void)uc;
env = uc->cpu->env_ptr;
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memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr));
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env->active_tc.PC = 0;
}
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int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
void *value = vals[i];
if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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*(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0];
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else {
switch(regid) {
default: break;
case UC_MIPS_REG_PC:
*(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
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break;
}
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}
}
return 0;
}
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int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
const void *value = vals[i];
if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(mipsreg_t *)value;
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else {
switch(regid) {
default: break;
case UC_MIPS_REG_PC:
MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(mipsreg_t *)value;
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// force to quit execution and flush TB
uc->quit_request = true;
uc_emu_stop(uc);
break;
}
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}
}
return 0;
}
DEFAULT_VISIBILITY
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#ifdef TARGET_MIPS64
#ifdef TARGET_WORDS_BIGENDIAN
void mips64_uc_init(struct uc_struct* uc)
#else
void mips64el_uc_init(struct uc_struct* uc)
#endif
#else // if TARGET_MIPS
#ifdef TARGET_WORDS_BIGENDIAN
void mips_uc_init(struct uc_struct* uc)
#else
void mipsel_uc_init(struct uc_struct* uc)
#endif
#endif
{
register_accel_types(uc);
mips_cpu_register_types(uc);
mips_machine_init(uc);
uc->reg_read = mips_reg_read;
uc->reg_write = mips_reg_write;
uc->reg_reset = mips_reg_reset;
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uc->release = mips_release;
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uc->set_pc = mips_set_pc;
uc->mem_redirect = mips_mem_redirect;
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uc_common_init(uc);
}