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unicorn/qemu/target/arm/a32.decode

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target/arm: Add stubs for aa32 decodetree Add the infrastructure that will become the new decoder. No instructions adjusted so far. Backports commit 51409b9e8cfe997b1ac3365df7400e0c6e844437 from qemu
2019-11-19 17:33:32 +00:00
# A32 conditional instructions
#
# Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
# All of the insn that have a COND field in insn[31:28] are here.
# All insns that have 0xf in insn[31:28] are in a32-uncond.decode.
#
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Backports commit 25ae32c558182c07fc6ad01b936e9151cbf00c44 from qemu
2019-11-19 17:39:45 +00:00
target/arm: Convert MSR (immediate) and hints Backports commit 6313059623dc512308681ba160ed862ac387e2fb from qemu
2019-11-20 00:56:43 +00:00
&empty
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Backports commit 25ae32c558182c07fc6ad01b936e9151cbf00c44 from qemu
2019-11-19 17:39:45 +00:00
&s_rrr_shi s rd rn rm shim shty
target/arm: Convert Data Processing (reg-shifted-reg) Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Backports commit 5be2c12337f4cbdbda4efe6ab485350f730faaad from qemu
2019-11-19 18:08:41 +00:00
&s_rrr_shr s rn rd rm rs shty
target/arm: Convert Data Processing (immediate) Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Backports commit 581c6ebd17c8f56ad52772216e6c6d8cc8997e8b from qemu
2019-11-19 18:13:53 +00:00
&s_rri_rot s rn rd imm rot
target/arm: Convert multiply and multiply accumulate Backports commit bd92fe353bda4412ffc46c0f7415207a684b45f2 from qemu
2019-11-19 18:32:45 +00:00
&s_rrrr s rd rn rm ra
&rrrr rd rn rm ra
target/arm: Convert Saturating addition and subtraction Backports commit 6d0730a82417e3a4a1911eb8e0246f3ba996f932 from qemu
2019-11-19 18:47:40 +00:00
&rrr rd rn rm
target/arm: Convert CLZ Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Backports commit 4c97f5b2f0fa9b37f9ff497f15411d809e6fd098 from qemu
2019-11-20 01:14:35 +00:00
&rr rd rm
target/arm: Convert T32 ADDW/SUBW Backports commit 145952e87fb86aaa9434d768c31eedbd323f7157 from qemu
2019-11-20 03:42:16 +00:00
&ri rd imm
target/arm: Convert BX, BXJ, BLX (register) Backports commit 4ed95abd700e43dee8e032f754b53bec2b047f75 from qemu
2019-11-20 01:11:56 +00:00
&r rm
target/arm: Convert the rest of A32 Miscelaneous instructions Backports commit 2cde9ea57dbc4cdee3677a1a335574537810fe2e from qemu
2019-11-20 03:38:16 +00:00
&i imm
target/arm: Convert MRS/MSR (banked, register) The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Backports commit d0b26644502103ca97093ef67749812dc1df7eea from qemu
2019-11-20 00:59:58 +00:00
&msr_reg rn r mask
&mrs_reg rd r
&msr_bank rn r sysm
&mrs_bank rd r sysm
target/arm: Convert load/store (register, immediate, literal) Backports commit 5e291fe16846d216d5a69569b1c59f497dff96e4 from qemu
2019-11-20 03:45:11 +00:00
&ldst_rr p w u rn rt rm shimm shtype
&ldst_ri p w u rn rt imm
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Backports commit 25ae32c558182c07fc6ad01b936e9151cbf00c44 from qemu
2019-11-19 17:39:45 +00:00
# Data-processing (register)
@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
&s_rrr_shi
@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
&s_rrr_shi rn=0
@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
&s_rrr_shi s=1 rd=0
AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi
EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi
SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi
RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi
ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi
ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi
SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi
RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi
TST_xrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi
TEQ_xrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi
CMP_xrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi
CMN_xrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi
ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi
MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi
BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi
MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi
target/arm: Convert Data Processing (reg-shifted-reg) Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Backports commit 5be2c12337f4cbdbda4efe6ab485350f730faaad from qemu
2019-11-19 18:08:41 +00:00
# Data-processing (register-shifted register)
@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
&s_rrr_shr
@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
&s_rrr_shr rn=0
@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
&s_rrr_shr rd=0 s=1
AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr
EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr
SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr
RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr
ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr
ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr
SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr
RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr
TST_xrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
TEQ_xrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
CMP_xrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
CMN_xrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr
MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr
BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr
MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr
target/arm: Convert Data Processing (immediate) Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Backports commit 581c6ebd17c8f56ad52772216e6c6d8cc8997e8b from qemu
2019-11-19 18:13:53 +00:00
# Data-processing (immediate)
%a32extrot 8:4 !function=times_2
@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \
&s_rri_rot rot=%a32extrot
@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \
&s_rri_rot rot=%a32extrot rn=0
@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \
&s_rri_rot rot=%a32extrot rd=0 s=1
AND_rri .... 001 0000 . .... .... ............ @s_rri_rot
EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot
SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot
RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot
ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot
ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot
SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot
RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot
TST_xri .... 001 1000 1 .... 0000 ............ @S_xri_rot
TEQ_xri .... 001 1001 1 .... 0000 ............ @S_xri_rot
CMP_xri .... 001 1010 1 .... 0000 ............ @S_xri_rot
CMN_xri .... 001 1011 1 .... 0000 ............ @S_xri_rot
ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot
MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot
BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot
MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot
target/arm: Convert multiply and multiply accumulate Backports commit bd92fe353bda4412ffc46c0f7415207a684b45f2 from qemu
2019-11-19 18:32:45 +00:00
# Multiply and multiply accumulate
@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr
@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0
@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr
target/arm: Convert Halfword multiply and multiply accumulate Backports commit 26c6923de7131fa1cf223ab67131d1992dc17001 from qemu
2019-11-19 18:52:23 +00:00
@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=0
target/arm: Convert multiply and multiply accumulate Backports commit bd92fe353bda4412ffc46c0f7415207a684b45f2 from qemu
2019-11-19 18:32:45 +00:00
MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn
MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn
UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn
MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn
UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn
UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn
SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn
SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn
target/arm: Convert Saturating addition and subtraction Backports commit 6d0730a82417e3a4a1911eb8e0246f3ba996f932 from qemu
2019-11-19 18:47:40 +00:00
# Saturating addition and subtraction
@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr
QADD .... 0001 0000 .... .... 0000 0101 .... @rndm
QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm
QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm
QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm
target/arm: Convert Halfword multiply and multiply accumulate Backports commit 26c6923de7131fa1cf223ab67131d1992dc17001 from qemu
2019-11-19 18:52:23 +00:00
# Halfword multiply and multiply accumulate
SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn
SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn
SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn
SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn
SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn
SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn
SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn
SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn
SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn
SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn
SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn
SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn
SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn
SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn
SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn
SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
target/arm: Convert MSR (immediate) and hints Backports commit 6313059623dc512308681ba160ed862ac387e2fb from qemu
2019-11-20 00:56:43 +00:00
# MSR (immediate) and hints
&msr_i r mask rot imm
@msr_i ---- .... .... mask:4 .... rot:4 imm:8 &msr_i
{
{
YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
WFE ---- 0011 0010 0000 1111 ---- 0000 0010
WFI ---- 0011 0010 0000 1111 ---- 0000 0011
# TODO: Implement SEV, SEVL; may help SMP performance.
# SEV ---- 0011 0010 0000 1111 ---- 0000 0100
# SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
# The canonical nop ends in 00000000, but the whole of the
# rest of the space executes as nop if otherwise unsupported.
NOP ---- 0011 0010 0000 1111 ---- ---- ----
}
# Note mask = 0 is covered by NOP
MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0
}
MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1
target/arm: Convert MRS/MSR (banked, register) The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Backports commit d0b26644502103ca97093ef67749812dc1df7eea from qemu
2019-11-20 00:59:58 +00:00
target/arm: Convert Cyclic Redundancy Check Backports commit 6c35d53f1bde7fe327c074473c3048d6e6f15e95 from qemu
2019-11-20 01:04:55 +00:00
# Cyclic Redundancy Check
CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm
CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm
CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm
CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm
CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm
CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm
target/arm: Convert MRS/MSR (banked, register) The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Backports commit d0b26644502103ca97093ef67749812dc1df7eea from qemu
2019-11-20 00:59:58 +00:00
# Miscellaneous instructions
%sysm 8:1 16:4
target/arm: Convert the rest of A32 Miscelaneous instructions Backports commit 2cde9ea57dbc4cdee3677a1a335574537810fe2e from qemu
2019-11-20 03:38:16 +00:00
%imm16_8_0 8:12 0:4
target/arm: Convert MRS/MSR (banked, register) The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Backports commit d0b26644502103ca97093ef67749812dc1df7eea from qemu
2019-11-20 00:59:58 +00:00
target/arm: Convert BX, BXJ, BLX (register) Backports commit 4ed95abd700e43dee8e032f754b53bec2b047f75 from qemu
2019-11-20 01:11:56 +00:00
@rm ---- .... .... .... .... .... .... rm:4 &r
target/arm: Convert CLZ Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Backports commit 4c97f5b2f0fa9b37f9ff497f15411d809e6fd098 from qemu
2019-11-20 01:14:35 +00:00
@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr
target/arm: Convert the rest of A32 Miscelaneous instructions Backports commit 2cde9ea57dbc4cdee3677a1a335574537810fe2e from qemu
2019-11-20 03:38:16 +00:00
@i16 ---- .... .... .... .... .... .... .... &i imm=%imm16_8_0
target/arm: Convert BX, BXJ, BLX (register) Backports commit 4ed95abd700e43dee8e032f754b53bec2b047f75 from qemu
2019-11-20 01:11:56 +00:00
target/arm: Convert MRS/MSR (banked, register) The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Backports commit d0b26644502103ca97093ef67749812dc1df7eea from qemu
2019-11-20 00:59:58 +00:00
MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm
MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm
MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg
MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg
target/arm: Convert BX, BXJ, BLX (register) Backports commit 4ed95abd700e43dee8e032f754b53bec2b047f75 from qemu
2019-11-20 01:11:56 +00:00
BX .... 0001 0010 1111 1111 1111 0001 .... @rm
BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm
BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm
target/arm: Convert CLZ Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Backports commit 4c97f5b2f0fa9b37f9ff497f15411d809e6fd098 from qemu
2019-11-20 01:14:35 +00:00
CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm
target/arm: Convert ERET Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path to make it clear exactly what's happening -- we hit ALUExceptionReturn along that path. Backports commit ef11bc3c461e2c650e8bef552146a4b08f81884e from qemu
2019-11-20 03:33:07 +00:00
target/arm: Convert the rest of A32 Miscelaneous instructions Backports commit 2cde9ea57dbc4cdee3677a1a335574537810fe2e from qemu
2019-11-20 03:38:16 +00:00
ERET ---- 0001 0110 0000 0000 0000 0110 1110
HLT .... 0001 0000 .... .... .... 0111 .... @i16
BKPT .... 0001 0010 .... .... .... 0111 .... @i16
HVC .... 0001 0100 .... .... .... 0111 .... @i16
SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i
target/arm: Convert load/store (register, immediate, literal) Backports commit 5e291fe16846d216d5a69569b1c59f497dff96e4 from qemu
2019-11-20 03:45:11 +00:00
# Load/Store Dual, Half, Signed Byte (register)
@ldst_rr_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... rm:4 \
&ldst_rr p=1 shimm=0 shtype=0
@ldst_rr_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... rm:4 \
&ldst_rr p=0 w=0 shimm=0 shtype=0
STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_pw0
STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p1w
LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_pw0
LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_p1w
STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_pw0
STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_p1w
LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_pw0
LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p1w
LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_pw0
LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p1w
LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_pw0
LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p1w
# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding,
# and act as normal post-indexed (P=0, W=0).
@ldst_rr_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... rm:4 \
&ldst_rr p=0 w=0 shimm=0 shtype=0
STRHT_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p0w1
LDRHT_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p0w1
LDRSBT_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p0w1
LDRSHT_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p0w1
# Load/Store word and unsigned byte (register)
@ldst_rs_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \
&ldst_rr p=1
@ldst_rs_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \
&ldst_rr p=0 w=0
STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_pw0
STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p1w
STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_pw0
STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p1w
LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_pw0
LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p1w
LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_pw0
LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p1w
@ldst_rs_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \
&ldst_rr p=0 w=0
STRT_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p0w1
STRBT_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p0w1
LDRT_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p0w1
LDRBT_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p0w1
# Load/Store Dual, Half, Signed Byte (immediate)
%imm8s_8_0 8:4 0:4
@ldst_ri8_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... .... \
&ldst_ri imm=%imm8s_8_0 p=1
@ldst_ri8_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... .... \
&ldst_ri imm=%imm8s_8_0 p=0 w=0
STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_pw0
STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p1w
LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_pw0
LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_p1w
STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_pw0
STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_p1w
LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_pw0
LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p1w
LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_pw0
LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p1w
LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_pw0
LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p1w
# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding,
# and act as normal post-indexed (P=0, W=0).
@ldst_ri8_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... .... \
&ldst_ri imm=%imm8s_8_0 p=0 w=0
STRHT_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p0w1
LDRHT_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p0w1
LDRSBT_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p0w1
LDRSHT_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p0w1
# Load/Store word and unsigned byte (immediate)
@ldst_ri12_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 imm:12 &ldst_ri p=1
@ldst_ri12_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0
STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p1w
STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_pw0
STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p1w
STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_pw0
LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p1w
LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_pw0
LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p1w
LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_pw0
@ldst_ri12_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0
STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1
STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1
LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1
LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1
Reference in a new issue Copy permalink