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15 lines
450 B
C
15 lines
450 B
C
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#ifndef HW_RISCV_SPIKE_H
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#define HW_RISCV_SPIKE_H
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#if defined(TARGET_RISCV32)
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#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
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#elif defined(TARGET_RISCV64)
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#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
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#endif
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void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc);
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#endif /* HW_RISCV_SPIKE_H */
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