2015-08-21 07:04:50 +00:00
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#ifndef GEN_ICOUNT_H
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2018-02-25 09:25:59 +00:00
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#define GEN_ICOUNT_H
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2015-08-21 07:04:50 +00:00
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#include "qemu/timer.h"
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/* Helpers for instruction counting code generation. */
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2018-03-05 21:01:13 +00:00
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//static TCGOp *icount_start_insn;
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2015-08-21 07:04:50 +00:00
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2018-03-04 19:25:10 +00:00
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static inline void gen_tb_start(TCGContext *tcg_ctx, TranslationBlock *tb)
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2015-08-21 07:04:50 +00:00
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{
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2019-04-22 09:52:41 +00:00
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//TCGv_i32 count, imm;
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2015-08-21 07:04:50 +00:00
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TCGv_i32 flag;
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tcg_ctx->exitreq_label = gen_new_label(tcg_ctx);
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flag = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->cpu_env,
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2019-06-13 19:32:36 +00:00
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offsetof(CPUState, tcg_exit_req) - offsetof(ArchCPU, env));
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2015-08-21 07:04:50 +00:00
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tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, flag, 0, tcg_ctx->exitreq_label);
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tcg_temp_free_i32(tcg_ctx, flag);
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#if 0
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2019-04-22 09:52:41 +00:00
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tcg_ctx->exitreq_label = gen_new_label();
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if (tb_cflags(tb) & CF_USE_ICOUNT) {
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2019-04-22 10:17:09 +00:00
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count = tcg_temp_local_new_i32(tcg_ctx);
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2019-04-22 09:52:41 +00:00
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} else {
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2019-04-22 10:17:09 +00:00
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count = tcg_temp_new_i32(tcg_ctx);
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2018-02-09 14:54:01 +00:00
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}
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2015-08-21 07:04:50 +00:00
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2019-04-22 10:17:09 +00:00
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tcg_gen_ld_i32(tcg_ctx, count, tcg_ctx->cpu_env,
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2019-06-13 19:32:36 +00:00
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offsetof(ArchCPU, neg.icount_decr.u32) -
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offsetof(ArchCPU, env));
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2019-04-22 09:52:41 +00:00
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if (tb_cflags(tb) & CF_USE_ICOUNT) {
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2019-04-22 10:17:09 +00:00
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imm = tcg_temp_new_i32(tcg_ctx);
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2019-04-22 09:52:41 +00:00
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/* We emit a movi with a dummy immediate argument. Keep the insn index
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* of the movi so that we later (when we know the actual insn count)
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* can update the immediate argument with the actual insn count. */
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2019-04-22 10:17:09 +00:00
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tcg_gen_movi_i32(tcg_ctx, imm, 0xdeadbeef);
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icount_start_insn = tcg_last_op(tcg_ctx);
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2019-04-22 09:52:41 +00:00
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2019-04-22 10:17:09 +00:00
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tcg_gen_sub_i32(tcg_ctx, count, count, imm);
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tcg_temp_free_i32(tcg_ctx, imm);
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2019-04-22 09:52:41 +00:00
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}
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2019-04-22 10:17:09 +00:00
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tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_LT, count, 0, tcg_ctx->exitreq_label);
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2019-04-22 09:52:41 +00:00
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if (tb_cflags(tb) & CF_USE_ICOUNT) {
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2019-04-22 10:17:09 +00:00
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tcg_gen_st16_i32(tcg_ctx, count, tcg_ctx, cpu_env,
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2019-06-13 19:32:36 +00:00
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offsetof(ArchCPU, neg.icount_decr.u16.low) -
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offsetof(ArchCPU, env));
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2019-04-22 09:52:41 +00:00
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}
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2019-04-22 10:17:09 +00:00
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tcg_temp_free_i32(tcg_ctx, count);
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2015-08-21 07:04:50 +00:00
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#endif
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}
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static inline void gen_tb_end(TCGContext *tcg_ctx, TranslationBlock *tb, int num_insns)
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{
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#if 0
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2019-04-22 09:52:41 +00:00
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if (tb_cflags(tb) & CF_USE_ICOUNT) {
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2018-02-24 01:01:15 +00:00
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/* Update the num_insn immediate parameter now that we know
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* the actual insn count. */
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2019-04-22 10:17:09 +00:00
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tcg_set_insn_param(tcg_ctx, icount_start_insn, 1, num_insns);
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2015-08-21 07:04:50 +00:00
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}
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#endif
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2019-04-22 09:52:41 +00:00
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gen_set_label(tcg_ctx, tcg_ctx->exitreq_label);
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tcg_gen_exit_tb(tcg_ctx, tb, TB_EXIT_REQUESTED);
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2015-08-21 07:04:50 +00:00
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}
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2018-03-04 02:08:51 +00:00
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static inline void gen_io_start(TCGContext *tcg_ctx)
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2015-08-21 07:04:50 +00:00
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{
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2019-06-13 19:32:36 +00:00
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#if 0
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2018-03-04 02:08:51 +00:00
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TCGv_i32 tmp = tcg_const_i32(tcg_ctx, 1);
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2019-06-13 19:32:36 +00:00
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tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->tcg_env,
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offsetof(ArchCPU, parent_obj.can_do_io) -
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offsetof(ArchCPU, env));
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2018-03-04 02:08:51 +00:00
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tcg_temp_free_i32(tcg_ctx, tmp);
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2019-06-13 19:32:36 +00:00
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#endif
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2015-08-21 07:04:50 +00:00
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}
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2018-03-04 02:08:51 +00:00
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static inline void gen_io_end(TCGContext *tcg_ctx)
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2015-08-21 07:04:50 +00:00
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{
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2019-06-13 19:32:36 +00:00
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#if 0
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2018-03-04 02:08:51 +00:00
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TCGv_i32 tmp = tcg_const_i32(tcg_ctx, 0);
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2019-06-13 19:32:36 +00:00
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tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->tcg_env,
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offsetof(ArchCPU, parent_obj.can_do_io) -
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offsetof(ArchCPU, env));
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2018-03-04 02:08:51 +00:00
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tcg_temp_free_i32(tcg_ctx, tmp);
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2015-08-21 07:04:50 +00:00
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#endif
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2019-06-13 19:32:36 +00:00
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}
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2015-08-21 07:04:50 +00:00
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#endif
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