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target/arm: Introduce pc_curr
Add a new field to retain the address of the instruction currently being translated. The 32-bit uses are all within subroutines used by a32 and t32. This will become less obvious when t16 support is merged with a32+t32, and having a clear definition will help. Convert aarch64 as well for consistency. Note that there is one instance of a pre-assert fprintf that used the wrong value for the address of the current instruction. Backports commit 43722a6d4f0c92f7e7e1e291580039b0f9789df1 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
1aa3c685a8
commit
0048f3e887
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@ -1425,7 +1425,7 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
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static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
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uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4;
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if (insn & (1U << 31)) {
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/* BL Branch with link */
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@ -1454,7 +1454,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
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sf = extract32(insn, 31, 1);
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op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
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rt = extract32(insn, 0, 5);
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addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
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addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
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tcg_cmp = read_cpu_reg(s, rt, sf);
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label_match = gen_new_label(tcg_ctx);
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@ -1484,7 +1484,7 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
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bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
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op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
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addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
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addr = s->pc_curr + sextract32(insn, 5, 14) * 4;
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rt = extract32(insn, 0, 5);
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tcg_cmp = tcg_temp_new_i64(tcg_ctx);
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@ -1516,7 +1516,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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return;
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}
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addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
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addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
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cond = extract32(insn, 0, 4);
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reset_btype(s);
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@ -1903,7 +1903,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
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TCGv_i32 tcg_syn, tcg_isread;
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uint32_t syndrome;
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gen_a64_set_pc_im(s, s->pc - 4);
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gen_a64_set_pc_im(s, s->pc_curr);
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tmpptr = tcg_const_ptr(tcg_ctx, ri);
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syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
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tcg_syn = tcg_const_i32(tcg_ctx, syndrome);
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@ -2072,7 +2072,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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/* The pre HVC helper handles cases when HVC gets trapped
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* as an undefined insn by runtime configuration.
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*/
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gen_a64_set_pc_im(s, s->pc - 4);
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gen_a64_set_pc_im(s, s->pc_curr);
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gen_helper_pre_hvc(tcg_ctx, tcg_ctx->cpu_env);
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gen_ss_advance(s);
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gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
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@ -2082,7 +2082,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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break;
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}
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gen_a64_set_pc_im(s, s->pc - 4);
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gen_a64_set_pc_im(s, s->pc_curr);
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tmp = tcg_const_i32(tcg_ctx, syn_aa64_smc(imm16));
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gen_helper_pre_smc(tcg_ctx, tcg_ctx->cpu_env, tmp);
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tcg_temp_free_i32(tcg_ctx, tmp);
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@ -2801,7 +2801,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
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tcg_rt = cpu_reg(s, rt);
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clean_addr = tcg_const_i64(tcg_ctx, (s->pc - 4) + imm);
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clean_addr = tcg_const_i64(tcg_ctx, s->pc_curr + imm);
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if (is_vector) {
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do_fp_ld(s, rt, clean_addr, size);
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} else {
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@ -3788,7 +3788,7 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
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offset = sextract64(insn, 5, 19);
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offset = offset << 2 | extract32(insn, 29, 2);
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rd = extract32(insn, 0, 5);
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base = s->pc - 4;
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base = s->pc_curr;
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if (page) {
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/* ADRP (page based) */
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@ -11828,7 +11828,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
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break;
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default:
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fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
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__func__, insn, fpopcode, s->pc);
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__func__, insn, fpopcode, s->pc_curr);
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g_assert_not_reached();
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}
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@ -14363,6 +14363,7 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
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return;
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}
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s->pc_curr = s->pc;
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insn = arm_ldl_code(env, s->pc, s->sctlr_b);
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s->insn = insn;
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s->pc += 4;
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@ -25,7 +25,7 @@ void unallocated_encoding(DisasContext *s);
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qemu_log_mask(LOG_UNIMP, \
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"%s:%d: unsupported instruction encoding 0x%08x " \
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"at pc=%016" PRIx64 "\n", \
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__FILE__, __LINE__, insn, s->pc - 4); \
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__FILE__, __LINE__, insn, s->pc_curr); \
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unallocated_encoding(s); \
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} while (0)
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@ -1269,7 +1269,7 @@ static inline void gen_hvc(DisasContext *s, int imm16)
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* as an undefined insn by runtime configuration (ie before
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* the insn really executes).
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*/
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gen_set_pc_im(s, s->pc - 4);
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gen_set_pc_im(s, s->pc_curr);
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gen_helper_pre_hvc(tcg_ctx, tcg_ctx->cpu_env);
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/* Otherwise we will treat this as a real exception which
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* happens after execution of the insn. (The distinction matters
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@ -1289,7 +1289,7 @@ static inline void gen_smc(DisasContext *s)
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TCGv_i32 tmp;
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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gen_set_pc_im(s, s->pc - 4);
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gen_set_pc_im(s, s->pc_curr);
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tmp = tcg_const_i32(tcg_ctx, syn_aa32_smc());
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gen_helper_pre_smc(tcg_ctx, tcg_ctx->cpu_env, tmp);
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tcg_temp_free_i32(tcg_ctx, tmp);
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@ -3310,7 +3310,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
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/* Sync state because msr_banked() can raise exceptions */
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc - 4);
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gen_set_pc_im(s, s->pc_curr);
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tcg_reg = load_reg(s, rn);
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tcg_tgtmode = tcg_const_i32(tcg_ctx, tgtmode);
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tcg_regno = tcg_const_i32(tcg_ctx, regno);
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@ -3333,7 +3333,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
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/* Sync state because mrs_banked() can raise exceptions */
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc - 4);
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gen_set_pc_im(s, s->pc_curr);
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tcg_reg = tcg_temp_new_i32(tcg_ctx);
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tcg_tgtmode = tcg_const_i32(tcg_ctx, tgtmode);
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tcg_regno = tcg_const_i32(tcg_ctx, regno);
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@ -7364,7 +7364,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
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}
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc - 4);
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gen_set_pc_im(s, s->pc_curr);
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tmpptr = tcg_const_ptr(tcg_ctx, ri);
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tcg_syn = tcg_const_i32(tcg_ctx, syndrome);
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tcg_isread = tcg_const_i32(tcg_ctx, isread);
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@ -7786,7 +7786,7 @@ static void gen_srs(DisasContext *s,
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tmp = tcg_const_i32(tcg_ctx, mode);
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/* get_r13_banked() will raise an exception if called from System mode */
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc - 4);
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gen_set_pc_im(s, s->pc_curr);
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gen_helper_get_r13_banked(tcg_ctx, addr, tcg_ctx->cpu_env, tmp);
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tcg_temp_free_i32(tcg_ctx, tmp);
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switch (amode) {
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@ -12232,6 +12232,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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return;
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}
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dc->pc_curr = dc->pc;
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insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
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dc->insn = insn;
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dc->pc += 4;
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@ -12301,6 +12302,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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return;
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}
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dc->pc_curr = dc->pc;
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insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
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is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
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dc->pc += 2;
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@ -10,6 +10,8 @@ typedef struct DisasContext {
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const ARMISARegisters *isar;
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target_ulong pc;
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/* The address of the current instruction being translated. */
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target_ulong pc_curr;
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target_ulong page_start;
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uint32_t insn;
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/* Nonzero if this instruction has been conditionally skipped. */
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