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target/arm: Update {fp,sve}_exception_el for VHE

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When TGE+E2H are both set, CPACR_EL1 is ignored.

Backports commit c2ddb7cf963b3bea838266bfca62514dc9750a10 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 16:25:59 -04:00 committed by Lioncash
parent 86d0163465
commit 01e1e7a3a0
1 changed files with 28 additions and 25 deletions
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15
qemu/target/arm/helper.c
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@ -5584,7 +5584,9 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
int sve_exception_el(CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
if (el <= 1) {
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
bool disabled = false;
/* The CPACR.ZEN controls traps to EL1:
@ -5599,8 +5601,7 @@ int sve_exception_el(CPUARMState *env, int el)
}
if (disabled) {
/* route_to_el2 */
return (arm_feature(env, ARM_FEATURE_EL2)
&& (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1);
return hcr_el2 & HCR_TGE ? 2 : 1;
}
/* Check CPACR.FPEN. */
@ -11557,8 +11558,6 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
int fp_exception_el(CPUARMState *env, int cur_el)
{
#ifndef CONFIG_USER_ONLY
int fpen;
/*
* CPACR and the CPTR registers don't exist before v6, so FP is
* always accessible
@ -11588,8 +11587,11 @@ int fp_exception_el(CPUARMState *env, int cur_el)
* 0, 2 : trap EL0 and EL1/PL1 accesses
* 1 : trap only EL0 accesses
* 3 : trap no accesses
* This register is ignored if E2H+TGE are both set.
*/
fpen = extract32(env->cp15.cpacr_el1, 20, 2);
if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
int fpen = extract32(env->cp15.cpacr_el1, 20, 2);
switch (fpen) {
case 0:
case 2:
@ -11613,6 +11615,7 @@ int fp_exception_el(CPUARMState *env, int cur_el)
case 3:
break;
}
}
/*
* The NSACR allows A-profile AArch32 EL3 and M-profile secure mode