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tcg-mips: Adjust move functions for mips64

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tcg_out_mov: using OPC_OR as most mips assemblers do;
tcg_out_movi: extended to 64-bit immediate.

Backports commit 2294d05dab503d11664e73712c7f250fd0bf9e3b from qemu
This commit is contained in:
Jin Guojie 2018-03-01 12:49:17 -05:00 committed by Lioncash
parent 00ccf9cec7
commit 022ff3580e
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 25 additions and 9 deletions
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34
qemu/tcg/mips/tcg-target.inc.c
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@ -544,23 +544,39 @@ static inline void tcg_out_mov(TCGContext *s, TCGType type,
{
/* Simple reg-reg move, optimising out the 'do nothing' case */
if (ret != arg) {
tcg_out_opc_reg(s, OPC_ADDU, ret, arg, TCG_REG_ZERO);
tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
}
}
static inline void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg reg, tcg_target_long arg)
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
arg = (int32_t)arg;
}
if (arg == (int16_t)arg) {
tcg_out_opc_imm(s, OPC_ADDIU, reg, TCG_REG_ZERO, arg);
} else if (arg == (uint16_t)arg) {
tcg_out_opc_imm(s, OPC_ORI, reg, TCG_REG_ZERO, arg);
tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
return;
}
if (arg == (uint16_t)arg) {
tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
return;
}
if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
} else {
tcg_out_opc_imm(s, OPC_LUI, reg, TCG_REG_ZERO, arg >> 16);
if (arg & 0xffff) {
tcg_out_opc_imm(s, OPC_ORI, reg, reg, arg & 0xffff);
tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
if (arg & 0xffff0000ull) {
tcg_out_dsll(s, ret, ret, 16);
tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
tcg_out_dsll(s, ret, ret, 16);
} else {
tcg_out_dsll(s, ret, ret, 32);
}
}
if (arg & 0xffff) {
tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
}
}
static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)