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target/arm: Implement SVE floating-point trig select coefficient
Backports commit a1f233f25fd502f9a5b40c14df1b4dbdda463487 from qemu
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@ -3356,6 +3356,9 @@
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#define helper_sve_fneg_d helper_sve_fneg_d_aarch64
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#define helper_sve_fneg_h helper_sve_fneg_h_aarch64
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#define helper_sve_fneg_s helper_sve_fneg_s_aarch64
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#define helper_sve_ftssel_d helper_sve_ftssel_d_aarch64
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#define helper_sve_ftssel_h helper_sve_ftssel_h_aarch64
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#define helper_sve_ftssel_s helper_sve_ftssel_s_aarch64
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#define helper_sve_index_b helper_sve_index_b_aarch64
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#define helper_sve_index_d helper_sve_index_d_aarch64
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#define helper_sve_index_h helper_sve_index_h_aarch64
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@ -3356,6 +3356,9 @@
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#define helper_sve_fneg_d helper_sve_fneg_d_aarch64eb
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#define helper_sve_fneg_h helper_sve_fneg_h_aarch64eb
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#define helper_sve_fneg_s helper_sve_fneg_s_aarch64eb
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#define helper_sve_ftssel_d helper_sve_ftssel_d_aarch64eb
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#define helper_sve_ftssel_h helper_sve_ftssel_h_aarch64eb
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#define helper_sve_ftssel_s helper_sve_ftssel_s_aarch64eb
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#define helper_sve_index_b helper_sve_index_b_aarch64eb
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#define helper_sve_index_d helper_sve_index_d_aarch64eb
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#define helper_sve_index_h helper_sve_index_h_aarch64eb
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@ -3377,6 +3377,9 @@ aarch64_symbols = (
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'helper_sve_fneg_d',
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'helper_sve_fneg_h',
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'helper_sve_fneg_s',
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'helper_sve_ftssel_d',
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'helper_sve_ftssel_h',
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'helper_sve_ftssel_s',
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'helper_sve_index_b',
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'helper_sve_index_d',
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'helper_sve_index_h',
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@ -389,6 +389,10 @@ DEF_HELPER_FLAGS_3(sve_fexpa_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_fexpa_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_fexpa_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_ftssel_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_ftssel_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_ftssel_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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@ -295,6 +295,10 @@ ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
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# Note esz != 0
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FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
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# SVE floating-point trig select coefficient
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# Note esz != 0
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FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
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### SVE Predicate Logical Operations Group
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# SVE predicate logical operations
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@ -23,6 +23,7 @@
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#include "exec/cpu_ldst.h"
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#include "exec/helper-proto.h"
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#include "tcg/tcg-gvec-desc.h"
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#include "fpu/softfloat.h"
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/* Note that vector data is stored in host-endian 64-bit chunks,
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so addressing units smaller than that needs a host-endian fixup. */
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@ -1191,3 +1192,45 @@ void HELPER(sve_fexpa_d)(void *vd, void *vn, uint32_t desc)
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d[i] = coeff[idx] | (exp << 52);
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}
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}
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void HELPER(sve_ftssel_h)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 2;
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uint16_t *d = vd, *n = vn, *m = vm;
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for (i = 0; i < opr_sz; i += 1) {
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uint16_t nn = n[i];
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uint16_t mm = m[i];
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if (mm & 1) {
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nn = float16_one;
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}
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d[i] = nn ^ (mm & 2) << 14;
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}
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}
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void HELPER(sve_ftssel_s)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 4;
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uint32_t *d = vd, *n = vn, *m = vm;
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for (i = 0; i < opr_sz; i += 1) {
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uint32_t nn = n[i];
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uint32_t mm = m[i];
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if (mm & 1) {
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nn = float32_one;
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}
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d[i] = nn ^ (mm & 2) << 30;
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}
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}
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void HELPER(sve_ftssel_d)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn, *m = vm;
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for (i = 0; i < opr_sz; i += 1) {
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uint64_t nn = n[i];
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uint64_t mm = m[i];
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if (mm & 1) {
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nn = float64_one;
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}
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d[i] = nn ^ (mm & 2) << 62;
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}
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}
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@ -976,6 +976,27 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a, uint32_t insn)
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return true;
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}
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static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
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{
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static gen_helper_gvec_3 * const fns[4] = {
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NULL,
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gen_helper_sve_ftssel_h,
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gen_helper_sve_ftssel_s,
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gen_helper_sve_ftssel_d,
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};
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if (a->esz == 0) {
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return false;
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}
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if (sve_access_check(s)) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned vsz = vec_full_reg_size(s);
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tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
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vec_full_reg_offset(s, a->rn),
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vec_full_reg_offset(s, a->rm),
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vsz, vsz, 0, fns[a->esz]);
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}
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return true;
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}
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/*
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*** SVE Predicate Logical Operations Group
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