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target/mips: Avoid case statements formulated by ranges - part 1

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Remove "range style" case statements to make code analysis easier.

This is needed also for some upcoming nanoMIPS-related refactorings.

Backports commit c2e19f3c2b1a1bb5f4fc3c55ee8cfa28dde9b810 from qemu
This commit is contained in:
Aleksandar Markovic 2018-08-17 14:14:01 -04:00 committed by Lioncash
parent a456920fd7
commit 0259ce5b6d
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 198 additions and 49 deletions
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247
qemu/target/mips/translate.c
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@ -5573,7 +5573,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 18: case 18:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_1e0i(tcg_ctx, mfc0_watchlo, arg, sel); gen_helper_1e0i(tcg_ctx, mfc0_watchlo, arg, sel);
rn = "WatchLo"; rn = "WatchLo";
break; break;
@ -5583,7 +5590,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 19: case 19:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel); gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel);
rn = "WatchHi"; rn = "WatchHi";
break; break;
@ -5709,7 +5723,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 27: case 27:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 0:
case 1:
case 2:
case 3:
tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */ tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */
rn = "CacheErr"; rn = "CacheErr";
break; break;
@ -5780,7 +5797,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE"; rn = "DESAVE";
break; break;
case 2: case 3: case 4: case 5: case 6: case 7: case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel)); CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2])); offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -6248,7 +6270,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 18: case 18:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel); gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel);
rn = "WatchLo"; rn = "WatchLo";
break; break;
@ -6258,7 +6287,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 19: case 19:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel); gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel);
rn = "WatchHi"; rn = "WatchHi";
break; break;
@ -6396,7 +6432,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 27: case 27:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 0:
case 1:
case 2:
case 3:
/* ignored */ /* ignored */
rn = "CacheErr"; rn = "CacheErr";
break; break;
@ -6462,7 +6501,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE"; rn = "DESAVE";
break; break;
case 2: case 3: case 4: case 5: case 6: case 7: case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel)); CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2])); offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -6924,7 +6968,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 18: case 18:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_1e0i(tcg_ctx, dmfc0_watchlo, arg, sel); gen_helper_1e0i(tcg_ctx, dmfc0_watchlo, arg, sel);
rn = "WatchLo"; rn = "WatchLo";
break; break;
@ -6934,7 +6985,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 19: case 19:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel); gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel);
rn = "WatchHi"; rn = "WatchHi";
break; break;
@ -7057,7 +7115,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 27: case 27:
switch (sel) { switch (sel) {
/* ignored */ /* ignored */
case 0: case 1: case 2: case 3: case 0:
case 1:
case 2:
case 3:
tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */ tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */
rn = "CacheErr"; rn = "CacheErr";
break; break;
@ -7122,7 +7183,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE"; rn = "DESAVE";
break; break;
case 2: case 3: case 4: case 5: case 6: case 7: case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel)); CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2])); offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -7581,7 +7647,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 18: case 18:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel); gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel);
rn = "WatchLo"; rn = "WatchLo";
break; break;
@ -7591,7 +7664,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 19: case 19:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel); gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel);
rn = "WatchHi"; rn = "WatchHi";
break; break;
@ -7725,7 +7805,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 27: case 27:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 0:
case 1:
case 2:
case 3:
/* ignored */ /* ignored */
rn = "CacheErr"; rn = "CacheErr";
break; break;
@ -7791,7 +7874,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE"; rn = "DESAVE";
break; break;
case 2: case 3: case 4: case 5: case 6: case 7: case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel)); CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2])); offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -7928,7 +8016,14 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
break; break;
case 16: case 16:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
gen_helper_mftc0_configx(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_const_tl(tcg_ctx, sel)); gen_helper_mftc0_configx(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_const_tl(tcg_ctx, sel));
break; break;
default: default:
@ -17377,7 +17472,10 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
case OPC_LSA: case OPC_LSA:
gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2)); gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
break; break;
case OPC_MULT: case OPC_MULTU: case OPC_DIV: case OPC_DIVU: case OPC_MULT:
case OPC_MULTU:
case OPC_DIV:
case OPC_DIVU:
op2 = MASK_R6_MULDIV(ctx->opcode); op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) { switch (op2) {
case R6_OPC_MUL: case R6_OPC_MUL:
@ -17433,7 +17531,11 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
} }
break; break;
case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU: case OPC_DMULT:
case OPC_DMULTU:
case OPC_DDIV:
case OPC_DDIVU:
op2 = MASK_R6_MULDIV(ctx->opcode); op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) { switch (op2) {
case R6_OPC_DMUL: case R6_OPC_DMUL:
@ -17512,7 +17614,10 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_muldiv(ctx, op1, 0, rs, rt); gen_muldiv(ctx, op1, 0, rs, rt);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU: case OPC_DMULT:
case OPC_DMULTU:
case OPC_DDIV:
case OPC_DDIVU:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
gen_muldiv(ctx, op1, 0, rs, rt); gen_muldiv(ctx, op1, 0, rs, rt);
@ -17580,7 +17685,10 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break; break;
} }
break; break;
case OPC_ADD: case OPC_ADDU: case OPC_SUB: case OPC_SUBU: case OPC_ADD:
case OPC_ADDU:
case OPC_SUB:
case OPC_SUBU:
gen_arith(ctx, op1, rd, rs, rt); gen_arith(ctx, op1, rd, rs, rt);
break; break;
case OPC_SLLV: /* Shifts */ case OPC_SLLV: /* Shifts */
@ -17616,7 +17724,11 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
case OPC_JALR: case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4); gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
break; break;
case OPC_TGE: case OPC_TGEU: case OPC_TLT: case OPC_TLTU: case OPC_TEQ: case OPC_TGE: /* Traps */
case OPC_TGEU:
case OPC_TLT:
case OPC_TLTU:
case OPC_TEQ:
case OPC_TNE: case OPC_TNE:
check_insn(ctx, ISA_MIPS2); check_insn(ctx, ISA_MIPS2);
gen_trap(ctx, op1, rs, rt, -1); gen_trap(ctx, op1, rs, rt, -1);
@ -17692,7 +17804,10 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break; break;
} }
break; break;
case OPC_DADD: case OPC_DADDU: case OPC_DSUB: case OPC_DSUBU: case OPC_DADD:
case OPC_DADDU:
case OPC_DSUB:
case OPC_DSUBU:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
gen_arith(ctx, op1, rd, rs, rt); gen_arith(ctx, op1, rd, rs, rt);
@ -17750,8 +17865,10 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL2(ctx->opcode); op1 = MASK_SPECIAL2(ctx->opcode);
switch (op1) { switch (op1) {
case OPC_MADD: case OPC_MADDU: /* Multiply and add/sub */ case OPC_MADD: /* Multiply and add/sub */
case OPC_MSUB: case OPC_MSUBU: case OPC_MADDU:
case OPC_MSUB:
case OPC_MSUBU:
check_insn(ctx, ISA_MIPS32); check_insn(ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rd & 3, rs, rt); gen_muldiv(ctx, op1, rd & 3, rs, rt);
break; break;
@ -17844,7 +17961,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
} }
op2 = MASK_BSHFL(ctx->opcode); op2 = MASK_BSHFL(ctx->opcode);
switch (op2) { switch (op2) {
case OPC_ALIGN: case OPC_ALIGN_END: case OPC_ALIGN:
case OPC_ALIGN_END:
gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3); gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
break; break;
case OPC_BITSWAP: case OPC_BITSWAP:
@ -17869,7 +17987,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
} }
op2 = MASK_DBSHFL(ctx->opcode); op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) { switch (op2) {
case OPC_DALIGN: case OPC_DALIGN_END: case OPC_DALIGN:
case OPC_DALIGN_END:
gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7); gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
break; break;
case OPC_DBITSWAP: case OPC_DBITSWAP:
@ -17900,9 +18019,12 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode); op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) { switch (op1) {
case OPC_DIV_G_2E: case OPC_DIVU_G_2E: case OPC_DIV_G_2E:
case OPC_MOD_G_2E: case OPC_MODU_G_2E: case OPC_DIVU_G_2E:
case OPC_MULT_G_2E: case OPC_MULTU_G_2E: case OPC_MOD_G_2E:
case OPC_MODU_G_2E:
case OPC_MULT_G_2E:
case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */ * the same mask and op1. */
if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) { if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
@ -18166,9 +18288,12 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E: case OPC_DDIV_G_2E:
case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: case OPC_DDIVU_G_2E:
case OPC_DMOD_G_2E: case OPC_DMODU_G_2E: case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E:
case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E); check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt); gen_loongson_integer(ctx, op1, rd, rs, rt);
break; break;
@ -18431,18 +18556,25 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
*/ */
if (ctx->eva) { if (ctx->eva) {
switch (op1) { switch (op1) {
case OPC_LWLE: case OPC_LWRE: case OPC_LWLE:
case OPC_LWRE:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */ /* fall through */
case OPC_LBUE: case OPC_LHUE: case OPC_LBUE:
case OPC_LBE: case OPC_LHE: case OPC_LLE: case OPC_LWE: case OPC_LHUE:
case OPC_LBE:
case OPC_LHE:
case OPC_LLE:
case OPC_LWE:
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
gen_ld(ctx, op1, rt, rs, imm); gen_ld(ctx, op1, rt, rs, imm);
return; return;
case OPC_SWLE: case OPC_SWRE: case OPC_SWLE:
case OPC_SWRE:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */ /* fall through */
case OPC_SBE: case OPC_SHE: case OPC_SBE:
case OPC_SHE:
case OPC_SWE: case OPC_SWE:
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
gen_st(ctx, op1, rt, rs, imm); gen_st(ctx, op1, rt, rs, imm);
@ -18474,7 +18606,8 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_BSHFL: case OPC_BSHFL:
op2 = MASK_BSHFL(ctx->opcode); op2 = MASK_BSHFL(ctx->opcode);
switch (op2) { switch (op2) {
case OPC_ALIGN: case OPC_ALIGN_END: case OPC_ALIGN:
case OPC_ALIGN_END:
case OPC_BITSWAP: case OPC_BITSWAP:
check_insn(ctx, ISA_MIPS32R6); check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx); decode_opc_special3_r6(env, ctx);
@ -18486,8 +18619,12 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DEXTM: case OPC_DEXTU: case OPC_DEXT: case OPC_DEXTM:
case OPC_DINSM: case OPC_DINSU: case OPC_DINS: case OPC_DEXTU:
case OPC_DEXT:
case OPC_DINSM:
case OPC_DINSU:
case OPC_DINS:
check_insn(ctx, ISA_MIPS64R2); check_insn(ctx, ISA_MIPS64R2);
check_mips_64(ctx); check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd); gen_bitops(ctx, op1, rt, rs, sa, rd);
@ -18495,7 +18632,8 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_DBSHFL: case OPC_DBSHFL:
op2 = MASK_DBSHFL(ctx->opcode); op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) { switch (op2) {
case OPC_DALIGN: case OPC_DALIGN_END: case OPC_DALIGN:
case OPC_DALIGN_END:
case OPC_DBITSWAP: case OPC_DBITSWAP:
check_insn(ctx, ISA_MIPS32R6); check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx); decode_opc_special3_r6(env, ctx);
@ -19758,7 +19896,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
} }
break; break;
case OPC_TGEI: case OPC_TGEIU: case OPC_TLTI: case OPC_TLTIU: case OPC_TEQI: /* REGIMM traps */ case OPC_TGEI: /* REGIMM traps */
case OPC_TGEIU:
case OPC_TLTI:
case OPC_TLTIU:
case OPC_TEQI:
case OPC_TNEI: case OPC_TNEI:
check_insn(ctx, ISA_MIPS2); check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
@ -19933,7 +20075,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
case OPC_XORI: case OPC_XORI:
gen_logic_imm(ctx, op, rt, rs, imm); gen_logic_imm(ctx, op, rt, rs, imm);
break; break;
case OPC_J: case OPC_JAL: /* Jump */ case OPC_J: /* Jump */
case OPC_JAL:
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
break; break;
@ -20000,15 +20143,19 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
case OPC_LWR: case OPC_LWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Fallthrough */ /* Fallthrough */
case OPC_LB: case OPC_LH: case OPC_LB:
case OPC_LW: case OPC_LBU: case OPC_LHU: case OPC_LH:
case OPC_LW:
case OPC_LBU:
case OPC_LHU:
gen_ld(ctx, op, rt, rs, imm); gen_ld(ctx, op, rt, rs, imm);
break; break;
case OPC_SWL: case OPC_SWL:
case OPC_SWR: case OPC_SWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */ /* fall through */
case OPC_SB: case OPC_SH: case OPC_SB:
case OPC_SH:
case OPC_SW: case OPC_SW:
gen_st(ctx, op, rt, rs, imm); gen_st(ctx, op, rt, rs, imm);
break; break;
@ -20279,7 +20426,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
/* MIPS64 opcodes */ /* MIPS64 opcodes */
case OPC_LDL: case OPC_LDR: case OPC_LDL:
case OPC_LDR:
case OPC_LLD: case OPC_LLD:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */ /* fall through */
@ -20289,7 +20437,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
check_mips_64(ctx); check_mips_64(ctx);
gen_ld(ctx, op, rt, rs, imm); gen_ld(ctx, op, rt, rs, imm);
break; break;
case OPC_SDL: case OPC_SDR: case OPC_SDL:
case OPC_SDR:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */ /* fall through */
case OPC_SD: case OPC_SD: