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target/riscv: csr: Remove compile time XLEN checks

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Backports 8987cdc48120c268568cdf87ba38591809d3efd1
This commit is contained in:
Alistair Francis 2021-03-08 15:34:28 -05:00 committed by Lioncash
parent 90abfa7c11
commit 037b9e3bd1
2 changed files with 64 additions and 63 deletions
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4
qemu/target/riscv/cpu_bits.h
View file

@ -437,9 +437,7 @@
#define HSTATUS_VGEIN 0x0003F000 #define HSTATUS_VGEIN 0x0003F000
#define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000 #define HSTATUS_VTSR 0x00400000
#if defined(TARGET_RISCV64) #define HSTATUS_VSXL 0x300000000
#define HSTATUS_VSXL 0x300000000
#endif
#define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL

123
qemu/target/riscv/csr.c
View file

@ -71,12 +71,31 @@ static int ctr(CPURISCVState *env, int csrno)
return 0; return 0;
} }
static int ctr32(CPURISCVState *env, int csrno)
{
if (!riscv_cpu_is_32bit(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
return ctr(env, csrno);
}
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
static int any(CPURISCVState *env, int csrno) static int any(CPURISCVState *env, int csrno)
{ {
return 0; return 0;
} }
static int any32(CPURISCVState *env, int csrno)
{
if (!riscv_cpu_is_32bit(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
return any(env, csrno);
}
static int smode(CPURISCVState *env, int csrno) static int smode(CPURISCVState *env, int csrno)
{ {
return -!riscv_has_ext(env, RVS); return -!riscv_has_ext(env, RVS);
@ -98,6 +117,16 @@ static int hmode(CPURISCVState *env, int csrno)
return -RISCV_EXCP_ILLEGAL_INST; return -RISCV_EXCP_ILLEGAL_INST;
} }
static int hmode32(CPURISCVState *env, int csrno)
{
if (!riscv_cpu_is_32bit(env)) {
return 0;
}
return hmode(env, csrno);
}
static int pmp(CPURISCVState *env, int csrno) static int pmp(CPURISCVState *env, int csrno)
{ {
return -!riscv_feature(env, RISCV_FEATURE_PMP); return -!riscv_feature(env, RISCV_FEATURE_PMP);
@ -250,7 +279,6 @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
return 0; return 0;
} }
#if defined(TARGET_RISCV32)
static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
{ {
// Unicorn: If'd out // Unicorn: If'd out
@ -267,7 +295,6 @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
#endif #endif
return 0; return 0;
} }
#endif /* TARGET_RISCV32 */
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
static int read_time(CPURISCVState *env, int csrno, target_ulong *val) static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
@ -277,14 +304,12 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
return 0; return 0;
} }
#if defined(TARGET_RISCV32)
static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
{ {
// Unicorn commented out // Unicorn commented out
//*val = cpu_get_host_ticks() >> 32; //*val = cpu_get_host_ticks() >> 32;
return 0; return 0;
} }
#endif
#else /* CONFIG_USER_ONLY */ #else /* CONFIG_USER_ONLY */
@ -300,7 +325,6 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
return 0; return 0;
} }
#if defined(TARGET_RISCV32)
static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
{ {
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
@ -312,7 +336,6 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
*val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
return 0; return 0;
} }
#endif
/* Machine constants */ /* Machine constants */
@ -351,19 +374,17 @@ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP; static const target_ulong vsip_writable_mask = MIP_VSSIP;
#if defined(TARGET_RISCV32) static const char valid_vm_1_10_32[16] = {
static const char valid_vm_1_10[16] = {
[VM_1_10_MBARE] = 1, [VM_1_10_MBARE] = 1,
[VM_1_10_SV32] = 1 [VM_1_10_SV32] = 1
}; };
#elif defined(TARGET_RISCV64)
static const char valid_vm_1_10[16] = { static const char valid_vm_1_10_64[16] = {
[VM_1_10_MBARE] = 1, [VM_1_10_MBARE] = 1,
[VM_1_10_SV39] = 1, [VM_1_10_SV39] = 1,
[VM_1_10_SV48] = 1, [VM_1_10_SV48] = 1,
[VM_1_10_SV57] = 1 [VM_1_10_SV57] = 1
}; };
#endif /* CONFIG_USER_ONLY */
/* Machine Information Registers */ /* Machine Information Registers */
static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
@ -386,7 +407,11 @@ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
static int validate_vm(CPURISCVState *env, target_ulong vm) static int validate_vm(CPURISCVState *env, target_ulong vm)
{ {
return valid_vm_1_10[vm & 0xf]; if (riscv_cpu_is_32bit(env)) {
return valid_vm_1_10_32[vm & 0xf];
} else {
return valid_vm_1_10_64[vm & 0xf];
}
} }
static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
@ -404,13 +429,13 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW; MSTATUS_TW;
#if defined(TARGET_RISCV64) if (!riscv_cpu_is_32bit(env)) {
/* /*
* RV32: MPV and GVA are not in mstatus. The current plan is to * RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it. * add them to mstatush. For now, we just don't support it.
*/ */
mask |= MSTATUS_MPV | MSTATUS_GVA; mask |= MSTATUS_MPV | MSTATUS_GVA;
#endif }
mstatus = (mstatus & ~mask) | (val & mask); mstatus = (mstatus & ~mask) | (val & mask);
@ -422,7 +447,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
return 0; return 0;
} }
#ifdef TARGET_RISCV32
static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
{ {
*val = env->mstatus >> 32; *val = env->mstatus >> 32;
@ -442,7 +466,6 @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
return 0; return 0;
} }
#endif
static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
{ {
@ -843,10 +866,10 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
{ {
*val = env->hstatus; *val = env->hstatus;
#ifdef TARGET_RISCV64 if (!riscv_cpu_is_32bit(env)) {
/* We only support 64-bit VSXL */ /* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2); *val = set_field(*val, HSTATUS_VSXL, 2);
#endif }
/* We only support little endian */ /* We only support little endian */
*val = set_field(*val, HSTATUS_VSBE, 0); *val = set_field(*val, HSTATUS_VSBE, 0);
return 0; return 0;
@ -855,11 +878,9 @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
{ {
env->hstatus = val; env->hstatus = val;
#ifdef TARGET_RISCV64 if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
if (get_field(val, HSTATUS_VSXL) != 2) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
} }
#endif
if (get_field(val, HSTATUS_VSBE) != 0) { if (get_field(val, HSTATUS_VSBE) != 0) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
} }
@ -1001,11 +1022,7 @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
return -RISCV_EXCP_ILLEGAL_INST; return -RISCV_EXCP_ILLEGAL_INST;
} }
#if defined(TARGET_RISCV32)
*val = env->htimedelta & 0xffffffff;
#else
*val = env->htimedelta; *val = env->htimedelta;
#endif
return 0; return 0;
} }
@ -1015,15 +1032,14 @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
return -RISCV_EXCP_ILLEGAL_INST; return -RISCV_EXCP_ILLEGAL_INST;
} }
#if defined(TARGET_RISCV32) if (riscv_cpu_is_32bit(env)) {
env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
#else } else {
env->htimedelta = val; env->htimedelta = val;
#endif }
return 0; return 0;
} }
#if defined(TARGET_RISCV32)
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val) static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
{ {
if (!env->rdtime_fn) { if (!env->rdtime_fn) {
@ -1043,7 +1059,6 @@ static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
return 0; return 0;
} }
#endif
/* Virtual CSR Registers */ /* Virtual CSR Registers */
static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
@ -1322,26 +1337,20 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Timers and Counters */ /* User Timers and Counters */
[CSR_CYCLE] = { ctr, read_instret }, [CSR_CYCLE] = { ctr, read_instret },
[CSR_INSTRET] = { ctr, read_instret }, [CSR_INSTRET] = { ctr, read_instret },
#if defined(TARGET_RISCV32) [CSR_CYCLEH] = { ctr32, read_instreth },
[CSR_CYCLEH] = { ctr, read_instreth }, [CSR_INSTRETH] = { ctr32, read_instreth },
[CSR_INSTRETH] = { ctr, read_instreth },
#endif
/* In privileged mode, the monitor will have to emulate TIME CSRs only if /* In privileged mode, the monitor will have to emulate TIME CSRs only if
* rdtime callback is not provided by machine/platform emulation */ * rdtime callback is not provided by machine/platform emulation */
[CSR_TIME] = { ctr, read_time }, [CSR_TIME] = { ctr, read_time },
#if defined(TARGET_RISCV32) [CSR_TIMEH] = { ctr32, read_timeh },
[CSR_TIMEH] = { ctr, read_timeh },
#endif
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */ /* Machine Timers and Counters */
[CSR_MCYCLE] = { any, read_instret }, [CSR_MCYCLE] = { any, read_instret },
[CSR_MINSTRET] = { any, read_instret }, [CSR_MINSTRET] = { any, read_instret },
#if defined(TARGET_RISCV32) [CSR_MCYCLEH] = { any32, read_instreth },
[CSR_MCYCLEH] = { any, read_instreth }, [CSR_MINSTRETH] = { any32, read_instreth },
[CSR_MINSTRETH] = { any, read_instreth },
#endif
/* Machine Information Registers */ /* Machine Information Registers */
[CSR_MVENDORID] = { any, read_zero }, [CSR_MVENDORID] = { any, read_zero },
@ -1358,9 +1367,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVEC] = { any, read_mtvec, write_mtvec }, [CSR_MTVEC] = { any, read_mtvec, write_mtvec },
[CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
#if defined(TARGET_RISCV32) [CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush },
[CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
#endif
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
@ -1400,9 +1407,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HGEIP] = { hmode, read_hgeip, write_hgeip }, [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, [CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta }, [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
#if defined(TARGET_RISCV32) [CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah},
[CSR_HTIMEDELTAH] = { hmode, read_htimedeltah, write_htimedeltah},
#endif
[CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus }, [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
[CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip }, [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
@ -1425,9 +1430,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
[CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
#if defined(TARGET_RISCV32) [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero },
[CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero },
[CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero },
#endif
#endif /* !CONFIG_USER_ONLY */ #endif /* !CONFIG_USER_ONLY */
}; };