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target-arm: Add VMPIDR_EL2

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Backports commit f0d574d63f4603ec431f16ad535a555bf7548b94 from qemu
This commit is contained in:
Edgar E. Iglesias 2018-02-15 12:52:24 -05:00 committed by Lioncash
parent 2b4c03224b
commit 03da6ff6db
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 19 additions and 2 deletions
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1
qemu/target-arm/cpu.h
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@ -390,6 +390,7 @@ typedef struct CPUARMState {
uint64_t c15_ccnt; uint64_t c15_ccnt;
uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */
uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
} cp15; } cp15;
struct { struct {

20
qemu/target-arm/helper.c
View file

@ -2168,6 +2168,13 @@ static uint64_t mpidr_read_val(CPUARMState *env)
static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{ {
unsigned int cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
return env->cp15.vmpidr_el2;
}
return mpidr_read_val(env); return mpidr_read_val(env);
} }
@ -3578,12 +3585,18 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, v8_cp_reginfo); define_arm_cp_regs(cpu, v8_cp_reginfo);
} }
if (arm_feature(env, ARM_FEATURE_EL2)) { if (arm_feature(env, ARM_FEATURE_EL2)) {
uint64_t vmpidr_def = mpidr_read_val(env);
ARMCPRegInfo vpidr_regs[] = { ARMCPRegInfo vpidr_regs[] = {
{ "VPIDR", 15,0,0, 0,4,0, ARM_CP_STATE_AA32, 0, { "VPIDR", 15,0,0, 0,4,0, ARM_CP_STATE_AA32, 0,
PL2_RW, 0, NULL, cpu->midr, offsetof(CPUARMState, cp15.vpidr_el2), {0, 0}, PL2_RW, 0, NULL, cpu->midr, offsetof(CPUARMState, cp15.vpidr_el2), {0, 0},
access_el3_aa32ns }, access_el3_aa32ns },
{ "VPIDR_EL2", 0,0,0, 3,4,0, ARM_CP_STATE_AA64, 0, { "VPIDR_EL2", 0,0,0, 3,4,0, ARM_CP_STATE_AA64, 0,
PL2_RW, 0, NULL, cpu->midr, offsetof(CPUARMState, cp15.vpidr_el2) }, PL2_RW, 0, NULL, cpu->midr, offsetof(CPUARMState, cp15.vpidr_el2) },
{ "VMPIDR", 15,0,0, 0,4,5, ARM_CP_STATE_AA32, 0,
PL2_RW, 0, NULL, vmpidr_def, offsetof(CPUARMState, cp15.vmpidr_el2), {0, 0},
access_el3_aa32ns },
{ "VMPIDR_EL2", 0,0,0, 3,4,5, ARM_CP_STATE_AA64, 0,
PL2_RW, 0, NULL, vmpidr_def, offsetof(CPUARMState, cp15.vmpidr_el2) },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, vpidr_regs);
@ -3601,13 +3614,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
* register the no_el2 reginfos. * register the no_el2 reginfos.
*/ */
if (arm_feature(env, ARM_FEATURE_EL3)) { if (arm_feature(env, ARM_FEATURE_EL3)) {
/* When EL3 exists but not EL2, VPIDR takes the value /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
* of MIDR_EL1. * of MIDR_EL1 and MPIDR_EL1.
*/ */
ARMCPRegInfo vpidr_regs[] = { ARMCPRegInfo vpidr_regs[] = {
{ "VPIDR_EL2", 0,0,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST, { "VPIDR_EL2", 0,0,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, cpu->midr, offsetof(CPUARMState, cp15.vpidr_el2), {0, 0}, PL2_RW, 0, NULL, cpu->midr, offsetof(CPUARMState, cp15.vpidr_el2), {0, 0},
access_el3_aa32ns_aa64any }, access_el3_aa32ns_aa64any },
{ "VMPIDR_EL2", 0,0,0, 3,4,5, ARM_CP_STATE_BOTH, ARM_CP_NO_RAW,
PL2_RW, 0, NULL, 0, 0, {0, 0},
access_el3_aa32ns_aa64any, mpidr_read, arm_cp_write_ignore },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, vpidr_regs);