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target/arm: Convert jazelle from feature bit to isar1 test
Having V6 alone imply jazelle was wrong for cortex-m0. Change to an assertion for V6 & !M. This was harmless, because the only place we tested ARM_FEATURE_JAZELLE was for 'bxj' in disas_arm(), which is unreachable for M-profile cores. Backports commit 09cbd50198d5dcac8bea2e47fa5dd641ec505fae from qemu
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4a58a81e31
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03e2d64aed
qemu/target/arm
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@ -633,8 +633,8 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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}
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5);
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set_feature(env, ARM_FEATURE_JAZELLE);
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if (!arm_feature(env, ARM_FEATURE_M)) {
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assert(cpu_isar_feature(jazelle, cpu));
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set_feature(env, ARM_FEATURE_AUXCR);
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}
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}
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@ -830,11 +830,16 @@ static void arm926_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
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set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
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cpu->midr = 0x41069265;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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/*
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* ARMv5 does not have the ID_ISAR registers, but we can still
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* set the field to indicate Jazelle support within QEMU.
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*/
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cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
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}
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static void arm946_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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@ -860,12 +865,18 @@ static void arm1026_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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set_feature(&cpu->env, ARM_FEATURE_AUXCR);
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
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set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
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cpu->midr = 0x4106a262;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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cpu->reset_auxcr = 1;
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/*
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* ARMv5 does not have the ID_ISAR registers, but we can still
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* set the field to indicate Jazelle support within QEMU.
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*/
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cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
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{
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
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ARMCPRegInfo ifar = { 0 };
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@ -1537,7 +1537,6 @@ enum arm_features {
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ARM_FEATURE_PMU, /* has PMU support */
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ARM_FEATURE_VBAR, /* has cp15 VBAR */
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ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
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ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
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ARM_FEATURE_SVE, /* has Scalable Vector Extension */
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ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
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ARM_FEATURE_M_MAIN, /* M profile Main Extension */
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@ -3098,6 +3097,11 @@ static inline bool isar_feature_arm_div(const ARMISARegisters *id)
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return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
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}
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static inline bool isar_feature_jazelle(const ARMISARegisters *id)
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{
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return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
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}
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static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
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{
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return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
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@ -41,7 +41,7 @@
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#define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
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/* currently all emulated v5 cores are also v5TE, so don't bother */
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#define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
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#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE)
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#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s)
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#define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
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#define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
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#define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
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