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target/riscv: Add Hypervisor machine CSRs accesses

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Backports commit 34cfb5f61842d495c6f6fc3eeb4197b5b44fd570 from qemu
This commit is contained in:
Alistair Francis 2020-03-22 01:26:45 -04:00 committed by Lioncash
parent dd356201a6
commit 042e3df075
1 changed files with 27 additions and 0 deletions
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27
qemu/target/riscv/csr.c
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@ -987,6 +987,30 @@ static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->mtval2;
return 0;
}
static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
{
env->mtval2 = val;
return 0;
}
static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->mtinst;
return 0;
}
static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
{
env->mtinst = val;
return 0;
}
/* Physical Memory Protection */
static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
{
@ -1208,6 +1232,9 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTVAL] = { hmode, read_vstval, write_vstval },
[CSR_VSATP] = { hmode, read_vsatp, write_vsatp },
[CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 },
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },