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target/arm: Reuse aa64_va_parameters for setting tbflags

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The arm_regime_tbi{0,1} functions are replacable with the new function
by giving the lowest and highest address.

Backports commit 5d8634f5a3a8474525edcfd581a659830e9e97c0 from qemu
This commit is contained in:
Richard Henderson 2019-01-22 16:29:42 -05:00 committed by Lioncash
parent 028aef155a
commit 048d8da45c
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GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 24 additions and 93 deletions
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2
qemu/aarch64.h
View file

@ -3286,8 +3286,6 @@
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64
#define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64
#define arm_mmu_idx arm_mmu_idx_aarch64
#define arm_regime_tbi0 arm_regime_tbi0_aarch64
#define arm_regime_tbi1 arm_regime_tbi1_aarch64
#define arm_register_pre_el_change_hook arm_register_pre_el_change_hook_aarch64
#define arm_register_el_change_hook arm_register_el_change_hook_aarch64
#define arm_reset_cpu arm_reset_cpu_aarch64

2
qemu/aarch64eb.h
View file

@ -3286,8 +3286,6 @@
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64eb
#define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64eb
#define arm_mmu_idx arm_mmu_idx_aarch64eb
#define arm_regime_tbi0 arm_regime_tbi0_aarch64eb
#define arm_regime_tbi1 arm_regime_tbi1_aarch64eb
#define arm_register_pre_el_change_hook arm_register_pre_el_change_hook_aarch64eb
#define arm_register_el_change_hook arm_register_el_change_hook_aarch64eb
#define arm_reset_cpu arm_reset_cpu_aarch64eb

2
qemu/arm.h
View file

@ -3278,8 +3278,6 @@
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm
#define arm_hcr_el2_eff arm_hcr_el2_eff_arm
#define arm_mmu_idx arm_mmu_idx_arm
#define arm_regime_tbi0 arm_regime_tbi0_arm
#define arm_regime_tbi1 arm_regime_tbi1_arm
#define arm_register_pre_el_change_hook arm_register_pre_el_change_hook_arm
#define arm_register_el_change_hook arm_register_el_change_hook_arm
#define arm_reset_cpu arm_reset_cpu_arm

2
qemu/armeb.h
View file

@ -3278,8 +3278,6 @@
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb
#define arm_hcr_el2_eff arm_hcr_el2_eff_armeb
#define arm_mmu_idx arm_mmu_idx_armeb
#define arm_regime_tbi0 arm_regime_tbi0_armeb
#define arm_regime_tbi1 arm_regime_tbi1_armeb
#define arm_register_pre_el_change_hook arm_register_pre_el_change_hook_armeb
#define arm_register_el_change_hook arm_register_el_change_hook_armeb
#define arm_reset_cpu arm_reset_cpu_armeb

4
qemu/header_gen.py
View file

@ -3287,8 +3287,6 @@ arm_symbols = (
'ARM_REGS_STORAGE_SIZE',
'arm_hcr_el2_eff',
'arm_mmu_idx',
'arm_regime_tbi0',
'arm_regime_tbi1',
'arm_register_pre_el_change_hook',
'arm_register_el_change_hook',
'arm_reset_cpu',
@ -3327,8 +3325,6 @@ aarch64_symbols = (
'arm_v7m_mmu_idx_for_secstate_and_priv',
'arm_hcr_el2_eff',
'arm_mmu_idx',
'arm_regime_tbi0',
'arm_regime_tbi1',
'arm_register_pre_el_change_hook',
'arm_register_el_change_hook',
'arm_reset_cpu',

35
qemu/target/arm/cpu.h
View file

@ -2996,41 +2996,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
}
#ifndef CONFIG_USER_ONLY
/**
* arm_regime_tbi0:
* @env: CPUARMState
* @mmu_idx: MMU index indicating required translation regime
*
* Extracts the TBI0 value from the appropriate TCR for the current EL
*
* Returns: the TBI0 value.
*/
uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
/**
* arm_regime_tbi1:
* @env: CPUARMState
* @mmu_idx: MMU index indicating required translation regime
*
* Extracts the TBI1 value from the appropriate TCR for the current EL
*
* Returns: the TBI1 value.
*/
uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
#else
/* We can't handle tagged addresses properly in user-only mode */
static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
{
return 0;
}
static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
{
return 0;
}
#endif
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags);

70
qemu/target/arm/helper.c
View file

@ -8160,48 +8160,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
return mmu_idx;
}
/* Returns TBI0 value for current regime el */
uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
{
TCR *tcr;
uint32_t el;
/* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
* a stage 1+2 mmu index into the appropriate stage 1 mmu index.
*/
mmu_idx = stage_1_mmu_idx(mmu_idx);
tcr = regime_tcr(env, mmu_idx);
el = regime_el(env, mmu_idx);
if (el > 1) {
return extract64(tcr->raw_tcr, 20, 1);
} else {
return extract64(tcr->raw_tcr, 37, 1);
}
}
/* Returns TBI1 value for current regime el */
uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
{
TCR *tcr;
uint32_t el;
/* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
* a stage 1+2 mmu index into the appropriate stage 1 mmu index.
*/
mmu_idx = stage_1_mmu_idx(mmu_idx);
tcr = regime_tcr(env, mmu_idx);
el = regime_el(env, mmu_idx);
if (el > 1) {
return 0;
} else {
return extract64(tcr->raw_tcr, 38, 1);
}
}
/* Return the TTBR associated with this translation regime */
static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
int ttbrn)
@ -12262,10 +12220,30 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
*pc = env->pc;
flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
/* Get control bits for tagged addresses */
flags = FIELD_DP32(flags, TBFLAG_A64, TBII,
(arm_regime_tbi1(env, mmu_idx) << 1) |
arm_regime_tbi0(env, mmu_idx));
#ifndef CONFIG_USER_ONLY
/*
* Get control bits for tagged addresses. Note that the
* translator only uses this for instruction addresses.
*/
{
ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
int tbii, tbid;
/* FIXME: ARMv8.1-VHE S2 translation regime. */
if (regime_el(env, stage1) < 2) {
ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
tbid = (p1.tbi << 1) | p0.tbi;
tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
} else {
tbid = p0.tbi;
tbii = tbid & !p0.tbid;
}
flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
}
#endif
if (cpu_isar_feature(aa64_sve, cpu)) {
int sve_el = sve_exception_el(env, current_el);