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tcg: Make cpu_dreg and cpu_areg TCGv arrays

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Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete.
This commit is contained in:
Lioncash 2018-02-21 00:13:11 -05:00
parent 6b19f43925
commit 04b743a26c
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 7 additions and 11 deletions
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14
qemu/target-m68k/translate.c
View file

@ -36,11 +36,11 @@
#define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
#define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
#define DREG(insn, pos) *((TCGv *)tcg_ctx->cpu_dregs[((insn) >> (pos)) & 7])
#define AREG(insn, pos) *((TCGv *)tcg_ctx->cpu_aregs[((insn) >> (pos)) & 7])
#define DREG(insn, pos) tcg_ctx->cpu_dregs[((insn) >> (pos)) & 7]
#define AREG(insn, pos) tcg_ctx->cpu_aregs[((insn) >> (pos)) & 7]
#define FREG(insn, pos) tcg_ctx->cpu_fregs[((insn) >> (pos)) & 7]
#define MACREG(acc) tcg_ctx->cpu_macc[acc]
#define QREG_SP *((TCGv *)tcg_ctx->cpu_aregs[7])
#define QREG_SP tcg_ctx->cpu_aregs[7]
#define IS_NULL_QREG(t) (TCGV_EQUAL(t, tcg_ctx->NULL_QREG))
@ -70,15 +70,11 @@ void m68k_tcg_init(struct uc_struct *uc)
for (i = 0; i < 8; i++) {
sprintf(p, "D%d", i);
if (!uc->init_tcg)
tcg_ctx->cpu_dregs[i] = g_malloc0(sizeof(TCGv));
*((TCGv *)tcg_ctx->cpu_dregs[i]) = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
tcg_ctx->cpu_dregs[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
offsetof(CPUM68KState, dregs[i]), p);
p += 3;
sprintf(p, "A%d", i);
if (!uc->init_tcg)
tcg_ctx->cpu_aregs[i] = g_malloc0(sizeof(TCGv));
*((TCGv *)tcg_ctx->cpu_aregs[i]) = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
tcg_ctx->cpu_aregs[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
offsetof(CPUM68KState, aregs[i]), p);
p += 3;
sprintf(p, "F%d", i);

4
qemu/tcg/tcg.h
View file

@ -774,8 +774,8 @@ struct TCGContext {
/* qemu/target-m68k/translate.c */
TCGv_i32 cpu_halted;
char cpu_reg_names[3*8*3 + 5*4];
void *cpu_dregs[8];
void *cpu_aregs[8];
TCGv cpu_dregs[8];
TCGv cpu_aregs[8];
TCGv_i64 cpu_fregs[8];
TCGv_i64 cpu_macc[4];
TCGv_i64 QREG_FP_RESULT;