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target-arm: Split AArch64 cases out of ats_write()

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Instead of simply reusing ats_write() as the handler for both AArch32
and AArch64 address translation operations, use a different function
for each with the common code in a third function. This is necessary
because the semantics for selecting the right translation regime are
different; we are only getting away with sharing currently because
we don't support EL2 and only support EL3 in AArch32.

Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
This commit is contained in:
Peter Maydell 2018-02-12 11:35:48 -05:00 committed by Lioncash
parent c0c5508a25
commit 04f30f91ed
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 26 additions and 7 deletions
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33
qemu/target-arm/helper.c
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@ -1228,13 +1228,13 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
return CP_ACCESS_OK;
}
static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
int access_type, int is_user)
{
hwaddr phys_addr;
target_ulong page_size;
int prot;
int ret, is_user = ri->opc2 & 2;
int access_type = ri->opc2 & 1;
int ret;
uint64_t par64;
ret = get_phys_addr(env, value, access_type, is_user,
@ -1274,9 +1274,28 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
((ret & 0xf) << 1) | 1;
}
}
return par64;
}
static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
int is_user = ri->opc2 & 2;
int access_type = ri->opc2 & 1;
uint64_t par64;
par64 = do_ats_write(env, value, access_type, is_user);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
int is_user = ri->opc2 & 2;
int access_type = ri->opc2 & 1;
env->cp15.par_el[1] = do_ats_write(env, value, access_type, is_user);
}
#endif
static const ARMCPRegInfo vapa_cp_reginfo[] = {
@ -1953,16 +1972,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
/* 64 bit address translation operations */
{ "AT_S1E1R", 0,7,8, 1,0,0, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, ats_write },
NULL, NULL, ats_write64 },
{ "AT_S1E1W", 0,7,8, 1,0,1, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, ats_write },
NULL, NULL, ats_write64 },
{ "AT_S1E0R", 0,7,8, 1,0,2, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, ats_write },
NULL, NULL, ats_write64 },
{ "AT_S1E0W", 0,7,8, 1,0,3, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, ats_write },
NULL, NULL, ats_write64 },
#endif
/* TLB invalidate last level of translation table walk */
{ "TLBIMVALIS", 15,8,3, 0,0,5, 0,