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target/mips/helper: Perform comparison pass with qemu

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Keeps code and formatting in sync with qemu
This commit is contained in:
Lioncash 2018-03-12 15:11:48 -04:00
parent 56675f5215
commit 05089ecb12
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 6 deletions
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10
qemu/target/mips/helper.c
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@ -204,8 +204,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
int *prot, target_ulong real_address, int *prot, target_ulong real_address,
int rw, int access_type, int mmu_idx) int rw, int access_type, int mmu_idx)
{ {
#if defined(TARGET_MIPS64)
/* User mode can only access useg/xuseg */ /* User mode can only access useg/xuseg */
#if defined(TARGET_MIPS64)
int user_mode = mmu_idx == MIPS_HFLAG_UM; int user_mode = mmu_idx == MIPS_HFLAG_UM;
int supervisor_mode = mmu_idx == MIPS_HFLAG_SM; int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
int kernel_mode = !user_mode && !supervisor_mode; int kernel_mode = !user_mode && !supervisor_mode;
@ -317,7 +317,6 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
access_type, mmu_idx, access_type, mmu_idx,
env->CP0_SegCtl0, 0x1FFFFFFF); env->CP0_SegCtl0, 0x1FFFFFFF);
} }
return ret; return ret;
} }
@ -783,6 +782,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
set_hflags_for_handler(env); set_hflags_for_handler(env);
break; break;
case EXCP_EXT_INTERRUPT: case EXCP_EXT_INTERRUPT:
cause = 0;
if (env->CP0_Cause & (1 << CP0Ca_IV)) { if (env->CP0_Cause & (1 << CP0Ca_IV)) {
uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f; uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
@ -803,7 +803,6 @@ void mips_cpu_do_interrupt(CPUState *cs)
/* Find the highest-priority interrupt. */ /* Find the highest-priority interrupt. */
while (pending >>= 1) { while (pending >>= 1) {
vector++; vector++;
} }
} }
offset = 0x200 + (vector * (spacing << 5)); offset = 0x200 + (vector * (spacing << 5));
@ -923,7 +922,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
goto set_EPC; goto set_EPC;
case EXCP_DWATCH: case EXCP_DWATCH:
cause = 23; cause = 23;
/* XXX: TODO: manage defered watch exceptions */ /* XXX: TODO: manage deferred watch exceptions */
goto set_EPC; goto set_EPC;
case EXCP_MCHECK: case EXCP_MCHECK:
cause = 24; cause = 24;
@ -989,7 +988,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
cs->exception_index = EXCP_NONE; cs->exception_index = EXCP_NONE;
} }
bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) // qq bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{ {
if (interrupt_request & CPU_INTERRUPT_HARD) { if (interrupt_request & CPU_INTERRUPT_HARD) {
MIPSCPU *cpu = MIPS_CPU(cs->uc, cs); MIPSCPU *cpu = MIPS_CPU(cs->uc, cs);
@ -1067,7 +1066,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
} }
#endif #endif
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
uint32_t exception, uint32_t exception,
int error_code, int error_code,