yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-02-02 10:51:06 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/mips: Increase 'supported ISAs/ASEs' flag holder size

Browse source 
Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.

Backports commit f9c9cd63e3dd84c5f052deec880ec92046bbe305 from qemu
This commit is contained in:
Philippe Mathieu-Daudé 2018-10-23 13:17:00 -04:00 committed by Lioncash
parent e52c27e21c
commit 055b2e4bdc
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 5 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
qemu/target/mips/cpu.h
View file

@ -811,7 +811,7 @@ struct CPUMIPSState {
int CCRes; /* Cycle count resolution/divisor */
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */
uint64_t insn_flags; /* Supported instruction set */
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;

2
qemu/target/mips/internal.h
View file

@ -59,7 +59,7 @@ struct mips_def_t {
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
target_ulong CP0_EBaseWG_rw_bitmask;
int insn_flags;
uint64_t insn_flags;
enum mips_mmu_types mmu_type;
};

6
qemu/target/mips/translate.c
View file

@ -1969,7 +1969,7 @@ typedef struct DisasContext {
target_ulong saved_pc;
target_ulong page_start;
uint32_t opcode;
int insn_flags;
uint64_t insn_flags;
int32_t CP0_Config1;
int32_t CP0_Config3;
int32_t CP0_Config5;
@ -2417,7 +2417,7 @@ static inline void check_dspr2(DisasContext *ctx)
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
static inline void check_insn(DisasContext *ctx, int flags)
static inline void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI);
@ -2427,7 +2427,7 @@ static inline void check_insn(DisasContext *ctx, int flags)
/* This code generates a "reserved instruction" exception if the
CPU has corresponding flag set which indicates that the instruction
has been removed. */
static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
{
if (unlikely(ctx->insn_flags & flags)) {
generate_exception_end(ctx, EXCP_RI);