yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-06-19 11:17:57 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL

Browse source 
The M-profile CONTROL register has two bits -- SFPA and FPCA --
which relate to floating-point support, and should be RES0 otherwise.
Handle them correctly in the MSR/MRS register access code.
Neither is banked between security states, so they are stored
in v7m.control[M_REG_S] regardless of current security state.

Backports commit 2e1c5bcd32014c9ede1b604ae6c2c653de17fc53 from qemu
This commit is contained in:
Peter Maydell 2019-04-30 10:21:21 -04:00 committed by Lioncash
parent c0cebeb5b5
commit 05add081a3
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
qemu/target/arm/helper.c
View file

@ -11838,7 +11838,14 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
return xpsr_read(env) & mask; return xpsr_read(env) & mask;
break; break;
case 20: /* CONTROL */ case 20: /* CONTROL */
return env->v7m.control[env->v7m.secure]; {
uint32_t value = env->v7m.control[env->v7m.secure];
if (!env->v7m.secure) {
/* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
}
return value;
}
case 0x94: /* CONTROL_NS */ case 0x94: /* CONTROL_NS */
/* We have to handle this here because unprivileged Secure code /* We have to handle this here because unprivileged Secure code
* can read the NS CONTROL register. * can read the NS CONTROL register.