mirror of
https://github.com/yuzu-emu/unicorn.git
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target/riscv: vector single-width floating-point add/subtract instructions
Backports ce2a0343f441f0ee949690eabae5ab600397e2eb
This commit is contained in:
LIU Zhiwei
Lioncash
parent
5fb589cdd7
commit
06092b88b9
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@ -6965,6 +6965,33 @@ riscv_symbols = (
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'helper_vnclip_vx_b',
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'helper_vnclip_vx_h',
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'helper_vnclip_vx_w',
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'helper_vfadd_vv_h',
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'helper_vfadd_vv_w',
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'helper_vfadd_vv_d',
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'helper_vfsub_vv_h',
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'helper_vfsub_vv_w',
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'helper_vfsub_vv_d',
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'helper_vfadd_vf_h',
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'helper_vfadd_vf_w',
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'helper_vfadd_vf_d',
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'helper_vfsub_vf_h',
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'helper_vfsub_vf_w',
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'helper_vfsub_vf_d',
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'helper_vfrsub_vf_h',
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'helper_vfrsub_vf_w',
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'helper_vfrsub_vf_d',
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'helper_vnsrl_vv_b',
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'helper_vnsrl_vv_h',
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'helper_vnsrl_vv_w',
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'helper_vnsra_vv_b',
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'helper_vnsra_vv_h',
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'helper_vnsra_vv_w',
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'helper_vnsrl_vx_b',
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'helper_vnsrl_vx_h',
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'helper_vnsrl_vx_w',
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'helper_vnsra_vx_b',
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'helper_vnsra_vx_h',
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'helper_vnsra_vx_w',
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'pmp_hart_has_privs',
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'pmpaddr_csr_read',
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'pmpaddr_csr_write',
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@ -4401,6 +4401,33 @@
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#define helper_vnclip_vx_b helper_vnclip_vx_b_riscv32
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#define helper_vnclip_vx_h helper_vnclip_vx_h_riscv32
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#define helper_vnclip_vx_w helper_vnclip_vx_w_riscv32
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#define helper_vfadd_vv_h helper_vfadd_vv_h_riscv32
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#define helper_vfadd_vv_w helper_vfadd_vv_w_riscv32
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#define helper_vfadd_vv_d helper_vfadd_vv_d_riscv32
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#define helper_vfsub_vv_h helper_vfsub_vv_h_riscv32
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#define helper_vfsub_vv_w helper_vfsub_vv_w_riscv32
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#define helper_vfsub_vv_d helper_vfsub_vv_d_riscv32
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#define helper_vfadd_vf_h helper_vfadd_vf_h_riscv32
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#define helper_vfadd_vf_w helper_vfadd_vf_w_riscv32
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#define helper_vfadd_vf_d helper_vfadd_vf_d_riscv32
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#define helper_vfsub_vf_h helper_vfsub_vf_h_riscv32
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#define helper_vfsub_vf_w helper_vfsub_vf_w_riscv32
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#define helper_vfsub_vf_d helper_vfsub_vf_d_riscv32
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#define helper_vfrsub_vf_h helper_vfrsub_vf_h_riscv32
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#define helper_vfrsub_vf_w helper_vfrsub_vf_w_riscv32
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#define helper_vfrsub_vf_d helper_vfrsub_vf_d_riscv32
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#define helper_vnsrl_vv_b helper_vnsrl_vv_b_riscv32
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#define helper_vnsrl_vv_h helper_vnsrl_vv_h_riscv32
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#define helper_vnsrl_vv_w helper_vnsrl_vv_w_riscv32
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#define helper_vnsra_vv_b helper_vnsra_vv_b_riscv32
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#define helper_vnsra_vv_h helper_vnsra_vv_h_riscv32
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#define helper_vnsra_vv_w helper_vnsra_vv_w_riscv32
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#define helper_vnsrl_vx_b helper_vnsrl_vx_b_riscv32
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#define helper_vnsrl_vx_h helper_vnsrl_vx_h_riscv32
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#define helper_vnsrl_vx_w helper_vnsrl_vx_w_riscv32
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#define helper_vnsra_vx_b helper_vnsra_vx_b_riscv32
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#define helper_vnsra_vx_h helper_vnsra_vx_h_riscv32
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#define helper_vnsra_vx_w helper_vnsra_vx_w_riscv32
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#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
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#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
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#define pmpaddr_csr_write pmpaddr_csr_write_riscv32
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@ -4401,6 +4401,33 @@
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#define helper_vnclip_vx_b helper_vnclip_vx_b_riscv64
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#define helper_vnclip_vx_h helper_vnclip_vx_h_riscv64
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#define helper_vnclip_vx_w helper_vnclip_vx_w_riscv64
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#define helper_vfadd_vv_h helper_vfadd_vv_h_riscv64
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#define helper_vfadd_vv_w helper_vfadd_vv_w_riscv64
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#define helper_vfadd_vv_d helper_vfadd_vv_d_riscv64
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#define helper_vfsub_vv_h helper_vfsub_vv_h_riscv64
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#define helper_vfsub_vv_w helper_vfsub_vv_w_riscv64
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#define helper_vfsub_vv_d helper_vfsub_vv_d_riscv64
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#define helper_vfadd_vf_h helper_vfadd_vf_h_riscv64
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#define helper_vfadd_vf_w helper_vfadd_vf_w_riscv64
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#define helper_vfadd_vf_d helper_vfadd_vf_d_riscv64
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#define helper_vfsub_vf_h helper_vfsub_vf_h_riscv64
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#define helper_vfsub_vf_w helper_vfsub_vf_w_riscv64
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#define helper_vfsub_vf_d helper_vfsub_vf_d_riscv64
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#define helper_vfrsub_vf_h helper_vfrsub_vf_h_riscv64
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#define helper_vfrsub_vf_w helper_vfrsub_vf_w_riscv64
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#define helper_vfrsub_vf_d helper_vfrsub_vf_d_riscv64
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#define helper_vnsrl_vv_b helper_vnsrl_vv_b_riscv64
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#define helper_vnsrl_vv_h helper_vnsrl_vv_h_riscv64
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#define helper_vnsrl_vv_w helper_vnsrl_vv_w_riscv64
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#define helper_vnsra_vv_b helper_vnsra_vv_b_riscv64
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#define helper_vnsra_vv_h helper_vnsra_vv_h_riscv64
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#define helper_vnsra_vv_w helper_vnsra_vv_w_riscv64
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#define helper_vnsrl_vx_b helper_vnsrl_vx_b_riscv64
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#define helper_vnsrl_vx_h helper_vnsrl_vx_h_riscv64
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#define helper_vnsrl_vx_w helper_vnsrl_vx_w_riscv64
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#define helper_vnsra_vx_b helper_vnsra_vx_b_riscv64
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#define helper_vnsra_vx_h helper_vnsra_vx_h_riscv64
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#define helper_vnsra_vx_w helper_vnsra_vx_w_riscv64
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#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
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#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
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#define pmpaddr_csr_write pmpaddr_csr_write_riscv64
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@ -436,6 +436,19 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmseq_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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@ -793,3 +806,19 @@ DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vfadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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@ -332,6 +332,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
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vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
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vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
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vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
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vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
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vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
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vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
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vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
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vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
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vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
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vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
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vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
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vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
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@ -439,6 +445,11 @@ vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm
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vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm
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vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm
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vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm
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vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
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vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
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vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
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vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
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vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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@ -1447,6 +1447,97 @@ GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
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GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
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GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
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/* Vector Narrowing Integer Right Shift Instructions */
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static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_reg(s, a->rs2, true) &&
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vext_check_reg(s, a->rs1, false) &&
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vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
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2 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3));
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}
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/* OPIVV with NARROW */
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#define GEN_OPIVV_NARROW_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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TCGContext *tcg_ctx = s->uc->tcg_ctx; \
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if (opivv_narrow_check(s, a)) { \
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uint32_t data = 0; \
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static gen_helper_gvec_4_ptr * const fns[3] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w, \
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}; \
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TCGLabel *over = gen_new_label(tcg_ctx); \
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); \
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\
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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tcg_gen_gvec_4_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), tcg_ctx->cpu_env, 0, \
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s->vlen / 8, data, fns[s->sew]); \
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gen_set_label(tcg_ctx, over); \
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return true; \
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} \
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return false; \
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}
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GEN_OPIVV_NARROW_TRANS(vnsra_vv)
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GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
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static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_reg(s, a->rs2, true) &&
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vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
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2 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3));
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}
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/* OPIVX with NARROW */
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#define GEN_OPIVX_NARROW_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (opivx_narrow_check(s, a)) { \
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static gen_helper_opivx * const fns[3] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w, \
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}; \
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return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
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} \
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return false; \
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}
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GEN_OPIVX_NARROW_TRANS(vnsra_vx)
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GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
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/* OPIVI with NARROW */
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#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (opivx_narrow_check(s, a)) { \
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static gen_helper_opivx * const fns[3] = { \
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gen_helper_##OPIVX##_b, \
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gen_helper_##OPIVX##_h, \
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gen_helper_##OPIVX##_w, \
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}; \
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return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
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fns[s->sew], s, ZX); \
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} \
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return false; \
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}
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GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
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GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
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/* Vector Integer Comparison Instructions */
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/*
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* For all comparison instructions, an illegal instruction exception is raised
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@ -1720,3 +1811,123 @@ GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
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GEN_OPIVX_NARROW_TRANS(vnclip_vx)
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GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
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GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
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/*
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*** Vector Float Point Arithmetic Instructions
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*/
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/* Vector Single-Width Floating-Point Add/Subtract Instructions */
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/*
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* If the current SEW does not correspond to a supported IEEE floating-point
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* type, an illegal instruction exception is raised.
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*/
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static bool opfvv_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_reg(s, a->rs2, false) &&
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vext_check_reg(s, a->rs1, false) &&
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(s->sew != 0));
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}
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/* OPFVV without GVEC IR */
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#define GEN_OPFVV_TRANS(NAME, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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TCGContext *tcg_ctx = s->uc->tcg_ctx; \
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if (CHECK(s, a)) { \
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||||
uint32_t data = 0; \
|
||||
static gen_helper_gvec_4_ptr * const fns[3] = { \
|
||||
gen_helper_##NAME##_h, \
|
||||
gen_helper_##NAME##_w, \
|
||||
gen_helper_##NAME##_d, \
|
||||
}; \
|
||||
TCGLabel *over = gen_new_label(tcg_ctx); \
|
||||
gen_set_rm(s, 7); \
|
||||
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); \
|
||||
\
|
||||
data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
|
||||
data = FIELD_DP32(data, VDATA, VM, a->vm); \
|
||||
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
|
||||
tcg_gen_gvec_4_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
|
||||
vreg_ofs(s, a->rs1), \
|
||||
vreg_ofs(s, a->rs2), tcg_ctx->cpu_env, 0, \
|
||||
s->vlen / 8, data, fns[s->sew - 1]); \
|
||||
gen_set_label(tcg_ctx, over); \
|
||||
return true; \
|
||||
} \
|
||||
return false; \
|
||||
}
|
||||
GEN_OPFVV_TRANS(vfadd_vv, opfvv_check)
|
||||
GEN_OPFVV_TRANS(vfsub_vv, opfvv_check)
|
||||
|
||||
typedef void gen_helper_opfvf(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr,
|
||||
TCGv_env, TCGv_i32);
|
||||
|
||||
static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
|
||||
uint32_t data, gen_helper_opfvf *fn, DisasContext *s)
|
||||
{
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
TCGv_ptr dest, src2, mask;
|
||||
TCGv_i32 desc;
|
||||
|
||||
TCGLabel *over = gen_new_label(tcg_ctx);
|
||||
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over);
|
||||
|
||||
dest = tcg_temp_new_ptr(tcg_ctx);
|
||||
mask = tcg_temp_new_ptr(tcg_ctx);
|
||||
src2 = tcg_temp_new_ptr(tcg_ctx);
|
||||
desc = tcg_const_i32(tcg_ctx, simd_desc(0, s->vlen / 8, data));
|
||||
|
||||
tcg_gen_addi_ptr(tcg_ctx, dest, tcg_ctx->cpu_env, vreg_ofs(s, vd));
|
||||
tcg_gen_addi_ptr(tcg_ctx, src2, tcg_ctx->cpu_env, vreg_ofs(s, vs2));
|
||||
tcg_gen_addi_ptr(tcg_ctx, mask, tcg_ctx->cpu_env, vreg_ofs(s, 0));
|
||||
|
||||
fn(tcg_ctx, dest, mask, tcg_ctx->cpu_fpr_risc[rs1], src2, tcg_ctx->cpu_env, desc);
|
||||
|
||||
tcg_temp_free_ptr(tcg_ctx, dest);
|
||||
tcg_temp_free_ptr(tcg_ctx, mask);
|
||||
tcg_temp_free_ptr(tcg_ctx, src2);
|
||||
tcg_temp_free_i32(tcg_ctx, desc);
|
||||
gen_set_label(tcg_ctx, over);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool opfvf_check(DisasContext *s, arg_rmrr *a)
|
||||
{
|
||||
/*
|
||||
* If the current SEW does not correspond to a supported IEEE floating-point
|
||||
* type, an illegal instruction exception is raised
|
||||
*/
|
||||
return (vext_check_isa_ill(s) &&
|
||||
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
|
||||
vext_check_reg(s, a->rd, false) &&
|
||||
vext_check_reg(s, a->rs2, false) &&
|
||||
(s->sew != 0));
|
||||
}
|
||||
|
||||
/* OPFVF without GVEC IR */
|
||||
#define GEN_OPFVF_TRANS(NAME, CHECK) \
|
||||
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
|
||||
{ \
|
||||
if (CHECK(s, a)) { \
|
||||
uint32_t data = 0; \
|
||||
static gen_helper_opfvf *const fns[3] = { \
|
||||
gen_helper_##NAME##_h, \
|
||||
gen_helper_##NAME##_w, \
|
||||
gen_helper_##NAME##_d, \
|
||||
}; \
|
||||
gen_set_rm(s, 7); \
|
||||
data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
|
||||
data = FIELD_DP32(data, VDATA, VM, a->vm); \
|
||||
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
|
||||
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
|
||||
fns[s->sew - 1], s); \
|
||||
} \
|
||||
return false; \
|
||||
}
|
||||
|
||||
GEN_OPFVF_TRANS(vfadd_vf, opfvf_check)
|
||||
GEN_OPFVF_TRANS(vfsub_vf, opfvf_check)
|
||||
GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include "exec/memop.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/helper-proto.h"
|
||||
#include "fpu/softfloat.h"
|
||||
#include "tcg/tcg-gvec-desc.h"
|
||||
#include "internals.h"
|
||||
#include <math.h>
|
||||
|
|
@ -1423,6 +1424,20 @@ GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
|
|||
GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
|
||||
GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
|
||||
|
||||
/* Vector Narrowing Integer Right Shift Instructions */
|
||||
GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
|
||||
GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
|
||||
GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
|
||||
GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
|
||||
GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
|
||||
GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
|
||||
GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
|
||||
GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
|
||||
GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
|
||||
GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
|
||||
GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
|
||||
GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
|
||||
|
||||
/* Vector Integer Comparison Instructions */
|
||||
#define DO_MSEQ(N, M) (N == M)
|
||||
#define DO_MSNE(N, M) (N != M)
|
||||
|
|
@ -3154,3 +3169,113 @@ RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
|
|||
GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb)
|
||||
GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh)
|
||||
GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl)
|
||||
|
||||
/*
|
||||
*** Vector Float Point Arithmetic Instructions
|
||||
*/
|
||||
/* Vector Single-Width Floating-Point Add/Subtract Instructions */
|
||||
#define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
|
||||
static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
|
||||
CPURISCVState *env) \
|
||||
{ \
|
||||
TX1 s1 = *((T1 *)vs1 + HS1(i)); \
|
||||
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
|
||||
*((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status); \
|
||||
}
|
||||
|
||||
#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \
|
||||
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
|
||||
void *vs2, CPURISCVState *env, \
|
||||
uint32_t desc) \
|
||||
{ \
|
||||
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
|
||||
uint32_t mlen = vext_mlen(desc); \
|
||||
uint32_t vm = vext_vm(desc); \
|
||||
uint32_t vl = env->vl; \
|
||||
uint32_t i; \
|
||||
\
|
||||
for (i = 0; i < vl; i++) { \
|
||||
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
|
||||
continue; \
|
||||
} \
|
||||
do_##NAME(vd, vs1, vs2, i, env); \
|
||||
} \
|
||||
CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
|
||||
}
|
||||
|
||||
RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
|
||||
RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
|
||||
RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
|
||||
GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2, clearh)
|
||||
GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4, clearl)
|
||||
GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8, clearq)
|
||||
|
||||
#define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
|
||||
static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
|
||||
CPURISCVState *env) \
|
||||
{ \
|
||||
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
|
||||
*((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
|
||||
}
|
||||
|
||||
#define GEN_VEXT_VF(NAME, ESZ, DSZ, CLEAR_FN) \
|
||||
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
|
||||
void *vs2, CPURISCVState *env, \
|
||||
uint32_t desc) \
|
||||
{ \
|
||||
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
|
||||
uint32_t mlen = vext_mlen(desc); \
|
||||
uint32_t vm = vext_vm(desc); \
|
||||
uint32_t vl = env->vl; \
|
||||
uint32_t i; \
|
||||
\
|
||||
for (i = 0; i < vl; i++) { \
|
||||
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
|
||||
continue; \
|
||||
} \
|
||||
do_##NAME(vd, s1, vs2, i, env); \
|
||||
} \
|
||||
CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
|
||||
}
|
||||
|
||||
RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
|
||||
RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
|
||||
RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
|
||||
GEN_VEXT_VF(vfadd_vf_h, 2, 2, clearh)
|
||||
GEN_VEXT_VF(vfadd_vf_w, 4, 4, clearl)
|
||||
GEN_VEXT_VF(vfadd_vf_d, 8, 8, clearq)
|
||||
|
||||
RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
|
||||
RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
|
||||
RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
|
||||
GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2, clearh)
|
||||
GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4, clearl)
|
||||
GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8, clearq)
|
||||
RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
|
||||
RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
|
||||
RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
|
||||
GEN_VEXT_VF(vfsub_vf_h, 2, 2, clearh)
|
||||
GEN_VEXT_VF(vfsub_vf_w, 4, 4, clearl)
|
||||
GEN_VEXT_VF(vfsub_vf_d, 8, 8, clearq)
|
||||
|
||||
static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
|
||||
{
|
||||
return float16_sub(b, a, s);
|
||||
}
|
||||
|
||||
static uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s)
|
||||
{
|
||||
return float32_sub(b, a, s);
|
||||
}
|
||||
|
||||
static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
|
||||
{
|
||||
return float64_sub(b, a, s);
|
||||
}
|
||||
|
||||
RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
|
||||
RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
|
||||
RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
|
||||
GEN_VEXT_VF(vfrsub_vf_h, 2, 2, clearh)
|
||||
GEN_VEXT_VF(vfrsub_vf_w, 4, 4, clearl)
|
||||
GEN_VEXT_VF(vfrsub_vf_d, 8, 8, clearq)
|
||||
|
|
|
|||
Loading…
Reference in a new issue