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target/arm: Create and use new function arm_v7m_is_handler_mode()

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Add a utility function for testing whether the CPU is in Handler
mode; this is just a check whether v7m.exception is non-zero, but
we do it in several places and it makes the code a bit easier
to read to not have to mentally figure out what the test is testing.

Backports commit 15b3f556bab4f961bf92141eb8521c8da3df5eb2 from qemu
This commit is contained in:
Peter Maydell 2018-03-04 13:06:39 -05:00 committed by Lioncash
parent a897ee919b
commit 06619904c6
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 12 additions and 6 deletions
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10
qemu/target/arm/cpu.h
View file

@ -1612,13 +1612,19 @@ static inline int arm_highest_el(CPUARMState *env)
return 1;
}
/* Return true if a v7M CPU is in Handler mode */
static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
{
return env->v7m.exception != 0;
}
/* Return the current Exception Level (as per ARMv8; note that this differs
* from the ARMv7 Privilege Level).
*/
static inline int arm_current_el(CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_M)) {
return !((env->v7m.exception == 0) && (env->v7m.control & 1));
return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1);
}
if (is_a64(env)) {
@ -2617,7 +2623,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
}
*flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
if (env->v7m.exception != 0) {
if (arm_v7m_is_handler_mode(env)) {
*flags |= ARM_TBFLAG_HANDLER_MASK;
}

8
qemu/target/arm/helper.c
View file

@ -5402,7 +5402,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
* that jumps to magic addresses don't have magic behaviour unless
* we're in Handler mode (compare pseudocode BXWritePC()).
*/
assert(env->v7m.exception != 0);
assert(arm_v7m_is_handler_mode(env));
/* In the spec pseudocode ExceptionReturn() is called directly
* from BXWritePC() and gets the full target PC value including
@ -5513,7 +5513,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
* resuming in Thread mode. If that doesn't match what the
* exception return type specified then this is a UsageFault.
*/
if (return_to_handler == (env->v7m.exception == 0)) {
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
/* Take an INVPC UsageFault by pushing the stack again. */
// Unicorn: commented out
//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
@ -5671,7 +5671,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
lr |= 4;
}
if (env->v7m.exception == 0) {
if (!arm_v7m_is_handler_mode(env)) {
lr |= 8;
}
@ -8074,7 +8074,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
* switch_v7m_sp() deals with updating the SPSEL bit in
* env->v7m.control, so we only need update the others.
*/
if (env->v7m.exception == 0) {
if (!arm_v7m_is_handler_mode(env)) {
switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
}
env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;