mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-01-22 05:51:06 +00:00
i386: Backport some formatting changes
This commit is contained in:
Lioncash
parent
8c0ed30d38
commit
067a459774
|
|
@ -2497,8 +2497,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|||
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
||||
CPUID_7_0_EBX_SMAP,
|
||||
.features[FEAT_7_0_ECX] =
|
||||
CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
|
||||
CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
|
||||
CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
|
||||
CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
|
||||
CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
|
||||
CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
|
||||
CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
|
||||
|
|
@ -2555,8 +2555,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|||
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
|
||||
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
|
||||
.features[FEAT_7_0_ECX] =
|
||||
CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
|
||||
CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
|
||||
CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
|
||||
CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
|
||||
CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
|
||||
CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
|
||||
CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
|
||||
|
|
|
|||
|
|
@ -622,64 +622,118 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
|
|||
#define CPUID_SVM_PAUSEFILTER (1U << 10)
|
||||
#define CPUID_SVM_PFTHRESHOLD (1U << 12)
|
||||
|
||||
#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
|
||||
#define CPUID_7_0_EBX_BMI1 (1U << 3)
|
||||
#define CPUID_7_0_EBX_HLE (1U << 4)
|
||||
#define CPUID_7_0_EBX_AVX2 (1U << 5)
|
||||
#define CPUID_7_0_EBX_SMEP (1U << 7)
|
||||
#define CPUID_7_0_EBX_BMI2 (1U << 8)
|
||||
#define CPUID_7_0_EBX_ERMS (1U << 9)
|
||||
#define CPUID_7_0_EBX_INVPCID (1U << 10)
|
||||
#define CPUID_7_0_EBX_RTM (1U << 11)
|
||||
#define CPUID_7_0_EBX_MPX (1U << 14)
|
||||
#define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
|
||||
#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
|
||||
#define CPUID_7_0_EBX_RDSEED (1U << 18)
|
||||
#define CPUID_7_0_EBX_ADX (1U << 19)
|
||||
#define CPUID_7_0_EBX_SMAP (1U << 20)
|
||||
#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
|
||||
#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
|
||||
#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
|
||||
#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
|
||||
#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
|
||||
#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
|
||||
#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
|
||||
#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
|
||||
#define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */
|
||||
#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
|
||||
#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
|
||||
/* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
|
||||
#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
|
||||
/* 1st Group of Advanced Bit Manipulation Extensions */
|
||||
#define CPUID_7_0_EBX_BMI1 (1U << 3)
|
||||
/* Hardware Lock Elision */
|
||||
#define CPUID_7_0_EBX_HLE (1U << 4)
|
||||
/* Intel Advanced Vector Extensions 2 */
|
||||
#define CPUID_7_0_EBX_AVX2 (1U << 5)
|
||||
/* Supervisor-mode Execution Prevention */
|
||||
#define CPUID_7_0_EBX_SMEP (1U << 7)
|
||||
/* 2nd Group of Advanced Bit Manipulation Extensions */
|
||||
#define CPUID_7_0_EBX_BMI2 (1U << 8)
|
||||
/* Enhanced REP MOVSB/STOSB */
|
||||
#define CPUID_7_0_EBX_ERMS (1U << 9)
|
||||
/* Invalidate Process-Context Identifier */
|
||||
#define CPUID_7_0_EBX_INVPCID (1U << 10)
|
||||
/* Restricted Transactional Memory */
|
||||
#define CPUID_7_0_EBX_RTM (1U << 11)
|
||||
/* Memory Protection Extension */
|
||||
#define CPUID_7_0_EBX_MPX (1U << 14)
|
||||
/* AVX-512 Foundation */
|
||||
#define CPUID_7_0_EBX_AVX512F (1U << 16)
|
||||
/* AVX-512 Doubleword & Quadword Instruction */
|
||||
#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
|
||||
/* Read Random SEED */
|
||||
#define CPUID_7_0_EBX_RDSEED (1U << 18)
|
||||
/* ADCX and ADOX instructions */
|
||||
#define CPUID_7_0_EBX_ADX (1U << 19)
|
||||
/* Supervisor Mode Access Prevention */
|
||||
#define CPUID_7_0_EBX_SMAP (1U << 20)
|
||||
/* AVX-512 Integer Fused Multiply Add */
|
||||
#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
|
||||
/* Persistent Commit */
|
||||
#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
|
||||
/* Flush a Cache Line Optimized */
|
||||
#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
|
||||
/* Cache Line Write Back */
|
||||
#define CPUID_7_0_EBX_CLWB (1U << 24)
|
||||
/* Intel Processor Trace */
|
||||
#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
|
||||
/* AVX-512 Prefetch */
|
||||
#define CPUID_7_0_EBX_AVX512PF (1U << 26)
|
||||
/* AVX-512 Exponential and Reciprocal */
|
||||
#define CPUID_7_0_EBX_AVX512ER (1U << 27)
|
||||
/* AVX-512 Conflict Detection */
|
||||
#define CPUID_7_0_EBX_AVX512CD (1U << 28)
|
||||
/* SHA1/SHA256 Instruction Extensions */
|
||||
#define CPUID_7_0_EBX_SHA_NI (1U << 29)
|
||||
/* AVX-512 Byte and Word Instructions */
|
||||
#define CPUID_7_0_EBX_AVX512BW (1U << 30)
|
||||
/* AVX-512 Vector Length Extensions */
|
||||
#define CPUID_7_0_EBX_AVX512VL (1U << 31)
|
||||
|
||||
#define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */
|
||||
#define CPUID_7_0_ECX_UMIP (1U << 2)
|
||||
#define CPUID_7_0_ECX_PKU (1U << 3)
|
||||
#define CPUID_7_0_ECX_OSPKE (1U << 4)
|
||||
#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
|
||||
#define CPUID_7_0_ECX_GFNI (1U << 8)
|
||||
#define CPUID_7_0_ECX_VAES (1U << 9)
|
||||
#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
|
||||
#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
|
||||
#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
|
||||
#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
|
||||
#define CPUID_7_0_ECX_LA57 (1U << 16)
|
||||
#define CPUID_7_0_ECX_RDPID (1U << 22)
|
||||
#define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */
|
||||
#define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */
|
||||
#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */
|
||||
/* AVX-512 Vector Byte Manipulation Instruction */
|
||||
#define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
|
||||
/* User-Mode Instruction Prevention */
|
||||
#define CPUID_7_0_ECX_UMIP (1U << 2)
|
||||
/* Protection Keys for User-mode Pages */
|
||||
#define CPUID_7_0_ECX_PKU (1U << 3)
|
||||
/* OS Enable Protection Keys */
|
||||
#define CPUID_7_0_ECX_OSPKE (1U << 4)
|
||||
/* UMONITOR/UMWAIT/TPAUSE Instructions */
|
||||
#define CPUID_7_0_ECX_WAITPKG (1U << 5)
|
||||
/* Additional AVX-512 Vector Byte Manipulation Instruction */
|
||||
#define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
|
||||
/* Galois Field New Instructions */
|
||||
#define CPUID_7_0_ECX_GFNI (1U << 8)
|
||||
/* Vector AES Instructions */
|
||||
#define CPUID_7_0_ECX_VAES (1U << 9)
|
||||
/* Carry-Less Multiplication Quadword */
|
||||
#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
|
||||
/* Vector Neural Network Instructions */
|
||||
#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
|
||||
/* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
|
||||
#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
|
||||
/* POPCNT for vectors of DW/QW */
|
||||
#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
|
||||
/* 5-level Page Tables */
|
||||
#define CPUID_7_0_ECX_LA57 (1U << 16)
|
||||
/* Read Processor ID */
|
||||
#define CPUID_7_0_ECX_RDPID (1U << 22)
|
||||
/* Cache Line Demote Instruction */
|
||||
#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
|
||||
/* Move Doubleword as Direct Store Instruction */
|
||||
#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
|
||||
/* Move 64 Bytes as Direct Store Instruction */
|
||||
#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
|
||||
|
||||
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
|
||||
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
|
||||
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
|
||||
#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
|
||||
#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/
|
||||
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
|
||||
/* AVX512 Neural Network Instructions */
|
||||
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
|
||||
/* AVX512 Multiply Accumulation Single Precision */
|
||||
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
|
||||
/* Speculation Control */
|
||||
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
|
||||
/* Arch Capabilities */
|
||||
#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
|
||||
/* Core Capability */
|
||||
#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
|
||||
/* Speculative Store Bypass Disable */
|
||||
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
|
||||
|
||||
#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */
|
||||
/* AVX512 BFloat16 Instruction */
|
||||
#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
|
||||
|
||||
#define KVM_HINTS_DEDICATED (1U << 0)
|
||||
|
||||
#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and do not invalidate cache */
|
||||
|
||||
#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
|
||||
/* CLZERO instruction */
|
||||
#define CPUID_8000_0008_EBX_CLZERO (1U << 0)
|
||||
/* Always save/restore FP error pointers */
|
||||
#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
|
||||
/* Write back and do not invalidate cache */
|
||||
#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
|
||||
/* Indirect Branch Prediction Barrier */
|
||||
#define CPUID_8000_0008_EBX_IBPB (1U << 12)
|
||||
|
||||
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
|
||||
#define CPUID_XSAVE_XSAVEC (1U << 1)
|
||||
|
|
|
|||
Loading…
Reference in a new issue