mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-01-22 05:41:04 +00:00
memory: split address_space_read and address_space_write
Rather than dispatching on is_write for every iteration, make address_space_rw call one of the two functions. The amount of duplicate logic is pretty small, and memory_access_is_direct can be tweaked so that it inlines better in the callers. Backports commit eb7eeb88628074207dd611472e712af775985e73 from qemu
This commit is contained in:
Paolo Bonzini
Lioncash
parent
077ffc3bd5
commit
0688343929
233
qemu/exec.c
233
qemu/exec.c
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@ -328,11 +328,10 @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
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static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
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static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
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{
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{
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if (memory_region_is_ram(mr)) {
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if (is_write) {
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return !(is_write && mr->readonly);
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return memory_region_is_ram(mr) && !mr->readonly;
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}
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} else {
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if (memory_region_is_romd(mr)) {
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return memory_region_is_ram(mr) || memory_region_is_romd(mr);
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return !is_write;
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}
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}
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return false;
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return false;
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@ -1796,8 +1795,8 @@ static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
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return l;
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return l;
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}
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}
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MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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uint8_t *buf, int len, bool is_write)
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const uint8_t *buf, int len)
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{
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{
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hwaddr l;
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hwaddr l;
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uint8_t *ptr;
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uint8_t *ptr;
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@ -1805,119 +1804,159 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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hwaddr addr1;
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hwaddr addr1;
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MemoryRegion *mr;
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MemoryRegion *mr;
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MemTxResult result = MEMTX_OK;
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MemTxResult result = MEMTX_OK;
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// Unicorn: commented out
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//bool release_lock = false;
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// Unicorn: commented out
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//rcu_read_lock();
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while (len > 0) {
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while (len > 0) {
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l = len;
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l = len;
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mr = address_space_translate(as, addr, &addr1, &l, is_write);
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mr = address_space_translate(as, addr, &addr1, &l, true);
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if (!mr)
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if (!mr)
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return true;
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return true;
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if (is_write) {
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if (!memory_access_is_direct(mr, true)) {
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if (!memory_access_is_direct(mr, is_write)) {
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// Unicorn: commented out
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l = memory_access_size(mr, l, addr1);
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//release_lock |= prepare_mmio_access(mr);
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/* XXX: could force current_cpu to NULL to avoid
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l = memory_access_size(mr, l, addr1);
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potential bugs */
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/* XXX: could force current_cpu to NULL to avoid
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switch (l) {
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potential bugs */
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case 8:
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switch (l) {
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/* 64 bit write access */
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case 8:
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val = ldq_p(buf);
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/* 64 bit write access */
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result |= memory_region_dispatch_write(mr, addr1, val, 8,
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val = ldq_p(buf);
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attrs);
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result |= memory_region_dispatch_write(mr, addr1, val, 8,
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break;
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attrs);
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case 4:
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break;
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/* 32 bit write access */
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case 4:
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val = ldl_p(buf);
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/* 32 bit write access */
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result |= memory_region_dispatch_write(mr, addr1, val, 4,
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val = ldl_p(buf);
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attrs);
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result |= memory_region_dispatch_write(mr, addr1, val, 4,
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attrs);
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break;
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break;
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case 2:
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case 2:
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/* 16 bit write access */
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/* 16 bit write access */
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val = lduw_p(buf);
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val = lduw_p(buf);
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result |= memory_region_dispatch_write(mr, addr1, val, 2,
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result |= memory_region_dispatch_write(mr, addr1, val, 2,
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attrs);
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attrs);
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break;
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break;
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case 1:
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case 1:
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/* 8 bit write access */
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/* 8 bit write access */
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val = ldub_p(buf);
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val = ldub_p(buf);
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result |= memory_region_dispatch_write(mr, addr1, val, 1,
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result |= memory_region_dispatch_write(mr, addr1, val, 1,
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attrs);
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attrs);
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break;
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break;
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default:
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default:
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abort();
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abort();
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}
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} else {
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addr1 += memory_region_get_ram_addr(mr);
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/* RAM case */
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ptr = qemu_get_ram_ptr(as->uc, addr1);
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memcpy(ptr, buf, l);
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invalidate_and_set_dirty(mr, addr1, l);
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}
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}
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} else {
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} else {
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if (!memory_access_is_direct(mr, is_write)) {
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addr1 += memory_region_get_ram_addr(mr);
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/* I/O case */
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/* RAM case */
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l = memory_access_size(mr, l, addr1);
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ptr = qemu_get_ram_ptr(mr->uc, addr1);
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memcpy(ptr, buf, l);
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switch (l) {
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invalidate_and_set_dirty(mr, addr1, l);
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case 8:
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/* 64 bit read access */
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result |= memory_region_dispatch_read(mr, addr1, &val, 8,
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attrs);
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stq_p(buf, val);
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break;
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case 4:
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/* 32 bit read access */
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result |= memory_region_dispatch_read(mr, addr1, &val, 4,
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attrs);
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stl_p(buf, val);
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break;
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case 2:
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/* 16 bit read access */
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result |= memory_region_dispatch_read(mr, addr1, &val, 2,
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attrs);
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stw_p(buf, val);
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break;
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case 1:
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/* 8 bit read access */
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result |= memory_region_dispatch_read(mr, addr1, &val, 1,
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attrs);
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stb_p(buf, val);
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break;
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default:
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abort();
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}
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} else {
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/* RAM case */
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ptr = qemu_get_ram_ptr(as->uc, mr->ram_addr + addr1);
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memcpy(buf, ptr, l);
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}
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}
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}
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/* Unicorn: commented out
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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release_lock = false;
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}*/
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len -= l;
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len -= l;
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buf += l;
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buf += l;
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addr += l;
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addr += l;
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}
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}
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// Unicorn: commented out
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//rcu_read_unlock();
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return result;
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return result;
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}
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}
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MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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const uint8_t *buf, int len)
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{
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return address_space_rw(as, addr, attrs, (uint8_t *)buf, len, true);
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}
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MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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uint8_t *buf, int len)
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uint8_t *buf, int len)
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{
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{
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return address_space_rw(as, addr, attrs, buf, len, false);
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hwaddr l;
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uint8_t *ptr;
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uint64_t val;
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hwaddr addr1;
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MemoryRegion *mr;
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MemTxResult result = MEMTX_OK;
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// Unicorn: commented out
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//bool release_lock = false;
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// Unicorn: commented out
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//rcu_read_lock();
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while (len > 0) {
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l = len;
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mr = address_space_translate(as, addr, &addr1, &l, false);
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if (!memory_access_is_direct(mr, false)) {
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/* I/O case */
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// Unicorn: commented out
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//release_lock |= prepare_mmio_access(mr);
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l = memory_access_size(mr, l, addr1);
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switch (l) {
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case 8:
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/* 64 bit read access */
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result |= memory_region_dispatch_read(mr, addr1, &val, 8,
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attrs);
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stq_p(buf, val);
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break;
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case 4:
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/* 32 bit read access */
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result |= memory_region_dispatch_read(mr, addr1, &val, 4,
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attrs);
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stl_p(buf, val);
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break;
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case 2:
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/* 16 bit read access */
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result |= memory_region_dispatch_read(mr, addr1, &val, 2,
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attrs);
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stw_p(buf, val);
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break;
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case 1:
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/* 8 bit read access */
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result |= memory_region_dispatch_read(mr, addr1, &val, 1,
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attrs);
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stb_p(buf, val);
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break;
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default:
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abort();
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}
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} else {
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/* RAM case */
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ptr = qemu_get_ram_ptr(mr->uc, mr->ram_addr + addr1);
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memcpy(buf, ptr, l);
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}
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/* Unicorn: Commented out
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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release_lock = false;
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}*/
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len -= l;
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buf += l;
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addr += l;
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}
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// Unicorn: commented out
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//rcu_read_unlock();
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return result;
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}
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}
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MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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uint8_t *buf, int len, bool is_write)
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{
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if (is_write) {
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return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
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} else {
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return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
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}
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}
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bool cpu_physical_memory_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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bool cpu_physical_memory_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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int len, int is_write)
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int len, int is_write)
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