yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-24 01:45:32 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Add isar_feature_aa32_vfp_simd

Browse source 
Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.

Backports commit 7fbc6a403a0aab834e764fa61d81ed8586cfe352 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 23:11:34 -04:00 committed by Lioncash
parent 764207865a
commit 06b52d6660
4 changed files with 15 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
qemu/target/arm/cpu.c
View file

@ -283,7 +283,7 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
} }
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;

9
qemu/target/arm/cpu.h
View file

@ -3323,6 +3323,15 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
} }
static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
{
/*
* Return true if either VFP or SIMD is implemented.
* In this case, a minimum of VFP w/ D0-D15.
*/
return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
}
static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
{ {
/* Return true if D16-D31 are implemented */ /* Return true if D16-D31 are implemented */

2
qemu/target/arm/helper.c
View file

@ -748,7 +748,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
*/ */
if (arm_feature(env, ARM_FEATURE_VFP)) { if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/* VFP coprocessor: cp10 & cp11 [23:20] */ /* VFP coprocessor: cp10 & cp11 [23:20] */
mask |= (1 << 31) | (1 << 30) | (0xf << 20); mask |= (1 << 31) | (1 << 30) | (0xf << 20);

7
qemu/target/arm/m_helper.c
View file

@ -662,7 +662,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
*/ */
uint32_t sig = 0xfefa125a; uint32_t sig = 0xfefa125a;
if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) { if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))
|| (lr & R_V7M_EXCRET_FTYPE_MASK)) {
sig |= 1; sig |= 1;
} }
return sig; return sig;
@ -764,7 +765,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
if (dotailchain) { if (dotailchain) {
/* Sanitize LR FType and PREFIX bits */ /* Sanitize LR FType and PREFIX bits */
if (!arm_feature(env, ARM_FEATURE_VFP)) { if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
lr |= R_V7M_EXCRET_FTYPE_MASK; lr |= R_V7M_EXCRET_FTYPE_MASK;
} }
lr = deposit32(lr, 24, 8, 0xff); lr = deposit32(lr, 24, 8, 0xff);
@ -1296,7 +1297,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
ftype = excret & R_V7M_EXCRET_FTYPE_MASK; ftype = excret & R_V7M_EXCRET_FTYPE_MASK;
if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) {
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception " qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "
"exit PC value 0x%" PRIx32 " is UNPREDICTABLE " "exit PC value 0x%" PRIx32 " is UNPREDICTABLE "
"if FPU not present\n", "if FPU not present\n",