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target/arm: Implement ID_PFR2

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This was defined at some point before ARMv8.4, and will
shortly be used by new processor descriptions.

Backports 1d51bc96cc4a9b2d31a3f4cb8442ce47753088e2
This commit is contained in:
Richard Henderson 2021-03-04 15:40:37 -05:00 committed by Lioncash
parent 5fb8ab10eb
commit 073923709f
2 changed files with 3 additions and 2 deletions
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1
qemu/target/arm/cpu.h
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@ -873,6 +873,7 @@ struct ARMCPU {
uint32_t id_mmfr4; uint32_t id_mmfr4;
uint32_t id_pfr0; uint32_t id_pfr0;
uint32_t id_pfr1; uint32_t id_pfr1;
uint32_t id_pfr2;
uint32_t mvfr0; uint32_t mvfr0;
uint32_t mvfr1; uint32_t mvfr1;
uint32_t mvfr2; uint32_t mvfr2;

4
qemu/target/arm/helper.c
View file

@ -7327,11 +7327,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3, .accessfn = access_aa64_tid3,
.resetvalue = 0 }, .resetvalue = 0 },
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3, .accessfn = access_aa64_tid3,
.resetvalue = 0 }, .resetvalue = cpu->isar.id_pfr2 },
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,