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https://github.com/yuzu-emu/unicorn.git
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target/arm: Move some functions used only in translate-neon.inc.c to that file
The functions neon_element_offset(), neon_load_element(), neon_load_element64(), neon_store_element() and neon_store_element64() are used only in the translate-neon.inc.c file, so move their definitions there. Since the .inc.c file is #included in translate.c this doesn't make much difference currently, but it's a more logical place to put the functions and it might be helpful if we ever decide to try to make the .inc.c files genuinely separate compilation units. Backports commit 6fb5787898aab6aa04887fed9cf3220dd4c3f36a from qemu
This commit is contained in:
Peter Maydell
Lioncash
parent
0b06317dc4
commit
083d207fb0
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@ -54,6 +54,111 @@ static inline int rsub_8(DisasContext *s, int x)
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#include "decode-neon-ls.inc.c"
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#include "decode-neon-shared.inc.c"
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/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
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* where 0 is the least significant end of the register.
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*/
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static inline long
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neon_element_offset(int reg, int element, MemOp size)
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{
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int element_size = 1 << size;
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int ofs = element * element_size;
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#ifdef HOST_WORDS_BIGENDIAN
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/* Calculate the offset assuming fully little-endian,
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* then XOR to account for the order of the 8-byte units.
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*/
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if (element_size < 8) {
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ofs ^= 8 - element_size;
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}
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#endif
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return neon_reg_offset(reg, 0) + ofs;
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}
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static void neon_load_element(DisasContext *s, TCGv_i32 var, int reg, int ele, MemOp mop)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
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switch (mop) {
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case MO_UB:
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tcg_gen_ld8u_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_UW:
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tcg_gen_ld16u_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_UL:
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tcg_gen_ld_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void neon_load_element64(DisasContext *s, TCGv_i64 var, int reg, int ele, MemOp mop)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
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switch (mop) {
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case MO_UB:
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tcg_gen_ld8u_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_UW:
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tcg_gen_ld16u_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_UL:
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tcg_gen_ld32u_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_Q:
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tcg_gen_ld_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void neon_store_element(DisasContext *s, int reg, int ele, MemOp size, TCGv_i32 var)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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long offset = neon_element_offset(reg, ele, size);
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switch (size) {
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case MO_8:
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tcg_gen_st8_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_16:
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tcg_gen_st16_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_32:
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tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void neon_store_element64(DisasContext *s, int reg, int ele, MemOp size, TCGv_i64 var)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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long offset = neon_element_offset(reg, ele, size);
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switch (size) {
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case MO_8:
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tcg_gen_st8_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_16:
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tcg_gen_st16_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_32:
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tcg_gen_st32_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_64:
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tcg_gen_st_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
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{
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int opr_sz;
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@ -1178,25 +1178,6 @@ neon_reg_offset (int reg, int n)
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return vfp_reg_offset(0, sreg);
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}
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/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
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* where 0 is the least significant end of the register.
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*/
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static inline long
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neon_element_offset(int reg, int element, MemOp size)
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{
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int element_size = 1 << size;
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int ofs = element * element_size;
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#ifdef HOST_WORDS_BIGENDIAN
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/* Calculate the offset assuming fully little-endian,
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* then XOR to account for the order of the 8-byte units.
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*/
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if (element_size < 8) {
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ofs ^= 8 - element_size;
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}
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#endif
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return neon_reg_offset(reg, 0) + ofs;
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}
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static TCGv_i32 neon_load_reg(DisasContext *s, int reg, int pass)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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@ -1205,49 +1186,6 @@ static TCGv_i32 neon_load_reg(DisasContext *s, int reg, int pass)
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return tmp;
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}
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static void neon_load_element(DisasContext *s, TCGv_i32 var, int reg, int ele, MemOp mop)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
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switch (mop) {
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case MO_UB:
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tcg_gen_ld8u_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_UW:
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tcg_gen_ld16u_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_UL:
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tcg_gen_ld_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void neon_load_element64(DisasContext *s, TCGv_i64 var, int reg, int ele, MemOp mop)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
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switch (mop) {
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case MO_UB:
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tcg_gen_ld8u_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_UW:
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tcg_gen_ld16u_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_UL:
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tcg_gen_ld32u_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_Q:
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tcg_gen_ld_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void neon_store_reg(DisasContext *s, int reg, int pass, TCGv_i32 var)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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@ -1255,49 +1193,6 @@ static void neon_store_reg(DisasContext *s, int reg, int pass, TCGv_i32 var)
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tcg_temp_free_i32(tcg_ctx, var);
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}
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static void neon_store_element(DisasContext *s, int reg, int ele, MemOp size, TCGv_i32 var)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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long offset = neon_element_offset(reg, ele, size);
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switch (size) {
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case MO_8:
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tcg_gen_st8_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_16:
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tcg_gen_st16_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_32:
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tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void neon_store_element64(DisasContext *s, int reg, int ele, MemOp size, TCGv_i64 var)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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long offset = neon_element_offset(reg, ele, size);
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switch (size) {
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case MO_8:
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tcg_gen_st8_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_16:
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tcg_gen_st16_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_32:
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tcg_gen_st32_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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case MO_64:
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tcg_gen_st_i64(tcg_ctx, var, tcg_ctx->cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static inline void neon_load_reg64(DisasContext *s, TCGv_i64 var, int reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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