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target/arm: Implement VFP fp16 VMOV between gp and halfprec registers
Implement the VFP fp16 variant of VMOV that transfers a 16-bit value between a general purpose register and a VFP register. Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later only we have no need to replicate the old "updates CPSR.NZCV" behaviour that the singleprec version of this insn does Backports commit 46a4b854525cb9f34a611f6ada6cdff1eab0ac2d
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@ -819,6 +819,41 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
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return true;
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return true;
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}
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}
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static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i32 tmp;
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if (!dc_isar_feature(aa32_fp16_arith, s)) {
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return false;
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}
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if (a->rt == 15) {
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/* UNPREDICTABLE; we choose to UNDEF */
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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if (a->l) {
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/* VFP to general purpose register */
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tmp = tcg_temp_new_i32(tcg_ctx);
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neon_load_reg32(s, tmp, a->vn);
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tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xffff);
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store_reg(s, a->rt, tmp);
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} else {
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/* general purpose register to VFP */
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tmp = load_reg(s, a->rt);
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tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xffff);
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neon_store_reg32(s, tmp, a->vn);
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tcg_temp_free_i32(tcg_ctx, tmp);
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}
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return true;
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}
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static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
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static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
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{
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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@ -74,6 +74,7 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
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vn=%vn_dp
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vn=%vn_dp
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VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
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VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
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VMOV_half ---- 1110 000 l:1 .... rt:4 1001 . 001 0000 vn=%vn_sp
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VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
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VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
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VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
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VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
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