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tcg/arm: Split out target constraints to tcg-target-con-str.h

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Backports 3440d583d64dedf82e2774b266bcae46253d6b06
This commit is contained in:
Richard Henderson 2021-03-04 15:56:52 -05:00 committed by Lioncash
parent 846fa770d6
commit 09890ddcb3
3 changed files with 42 additions and 55 deletions
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22
qemu/tcg/arm/tcg-target-con-str.h Normal file
View file

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: MIT */
/*
* Define Arm target-specific operand constraints.
* Copyright (c) 2021 Linaro
*/
/*
* Define constraint letters for register sets:
* REGS(letter, register_mask)
*/
REGS('r', ALL_GENERAL_REGS)
REGS('l', ALL_QLOAD_REGS)
REGS('s', ALL_QSTORE_REGS)
/*
* Define constraint letters for constants:
* CONST(letter, TCG_CT_CONST_* bit set)
*/
CONST('I', TCG_CT_CONST_ARM)
CONST('K', TCG_CT_CONST_INV)
CONST('N', TCG_CT_CONST_NEG)
CONST('Z', TCG_CT_CONST_ZERO)

2
qemu/tcg/arm/tcg-target.h
View file

@ -147,5 +147,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
#define TCG_TARGET_CON_STR_H
#endif

73
qemu/tcg/arm/tcg-target.inc.c
View file

@ -234,64 +234,27 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
#define TCG_CT_CONST_NEG 0x400
#define TCG_CT_CONST_ZERO 0x800
/* parse target specific constraints */
static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type)
{
switch (*ct_str++) {
case 'I':
ct->ct |= TCG_CT_CONST_ARM;
break;
case 'K':
ct->ct |= TCG_CT_CONST_INV;
break;
case 'N': /* The gcc constraint letter is L, already used here. */
ct->ct |= TCG_CT_CONST_NEG;
break;
case 'Z':
ct->ct |= TCG_CT_CONST_ZERO;
break;
#define ALL_GENERAL_REGS 0xffffu
case 'r':
ct->regs = 0xffff;
break;
/* qemu_ld address */
case 'l':
ct->regs = 0xffff;
/*
* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
* and r0-r1 doing the byte swapping, so don't use these.
* r3 is removed for softmmu to avoid clashes with helper arguments.
*/
#ifdef CONFIG_SOFTMMU
/* r0-r2,lr will be overwritten when reading the tlb entry,
so don't use these. */
tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
#define ALL_QLOAD_REGS \
(ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
(1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
(1 << TCG_REG_R14)))
#define ALL_QSTORE_REGS \
(ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
(1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \
((TARGET_LONG_BITS == 64) << TCG_REG_R3)))
#else
#define ALL_QLOAD_REGS ALL_GENERAL_REGS
#define ALL_QSTORE_REGS \
(ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1)))
#endif
break;
/* qemu_st address & data */
case 's':
ct->regs = 0xffff;
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
and r0-r1 doing the byte swapping, so don't use these. */
tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
#if defined(CONFIG_SOFTMMU)
/* Avoid clashes with registers being used for helper args */
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
#if TARGET_LONG_BITS == 64
/* Avoid clashes with registers being used for helper args */
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#endif
tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
#endif
break;
default:
return NULL;
}
return ct_str;
}
static inline uint32_t rotl(uint32_t val, int n)
{