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target/arm: Flush tlbs for E2&0 translation regime

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Backports commit 85d0dc9fa205027554372367f6925749a2d2b4c4 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 16:22:45 -04:00 committed by Lioncash
parent 50ac89852a
commit 0c03fa2dac
1 changed files with 18 additions and 7 deletions
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25
qemu/target/arm/helper.c
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@ -3949,8 +3949,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
static int vae1_tlbmask(CPUARMState *env) static int vae1_tlbmask(CPUARMState *env)
{ {
/* Since we exclude secure first, we may read HCR_EL2 directly. */
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
} else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
== (HCR_E2H | HCR_TGE)) {
return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0;
} else { } else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
} }
@ -3999,6 +4003,12 @@ static int alle1_tlbmask(CPUARMState *env)
} }
} }
static int e2_tlbmask(CPUARMState *env)
{
/* TODO: ARMv8.4-SecEL2 */
return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2;
}
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
@ -4011,10 +4021,10 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
ARMCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env);
CPUState *cs = CPU(cpu); int mask = e2_tlbmask(env);
tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); tlb_flush_by_mmuidx(cs, mask);
} }
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -4044,8 +4054,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
// UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0 #if 0
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
int mask = e2_tlbmask(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
#endif #endif
} }
@ -4067,11 +4078,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
* Currently handles both VAE2 and VALE2, since we don't support * Currently handles both VAE2 and VALE2, since we don't support
* flush-last-level-only. * flush-last-level-only.
*/ */
ARMCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env);
CPUState *cs = CPU(cpu); int mask = e2_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
} }
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,