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target-arm: Add AArch32 banked register access to secure physical timer

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If EL3 is AArch32, then the secure physical timer is accessed via
banking of the registers used for the non-secure physical timer.
Implement this banking.

Note that the access controls for the AArch32 banked registers
remain the same as the physical-timer checks; they are not the
same as the controls on the AArch64 secure timer registers.

Backports commit 9ff9dd3c875956523bb4c19ca712e5d05aab3c65 from qemu
This commit is contained in:
Peter Maydell 2018-02-14 20:50:27 -05:00 committed by Lioncash
parent 6c24603b23
commit 0c3e33ee11
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 3 deletions
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15
qemu/target-arm/helper.c
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@ -1362,8 +1362,11 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_cntkctl), },
/* per-timer control */
{ "CNTP_CTL", 15,14,2, 0,0,1, 0,
ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), {0, 0},
ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, ARM_CP_SECSTATE_NS, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), {0, 0},
gt_ptimer_access, NULL, gt_phys_ctl_write, NULL, raw_write, NULL },
{ "CNTP_CTL(S)", 15,14,2, 0,0,1, 0, ARM_CP_IO | ARM_CP_ALIAS,
PL1_RW | PL0_R, ARM_CP_SECSTATE_S, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), {0, 0},
gt_ptimer_access, NULL, gt_sec_ctl_write, NULL, raw_write },
{ "CNTP_CTL_EL0", 0,14,2, 3,3,1, ARM_CP_STATE_AA64,
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), {0, 0},
gt_ptimer_access, NULL,gt_phys_ctl_write, NULL,raw_write, },
@ -1375,8 +1378,11 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
gt_vtimer_access, NULL,gt_virt_ctl_write, NULL,raw_write, },
/* TimerValue views: a 32 bit downcounting view of the underlying state */
{ "CNTP_TVAL", 15,14,2, 0,0,0, 0,
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, ARM_CP_SECSTATE_NS, NULL, 0, 0, {0, 0},
gt_ptimer_access, gt_phys_tval_read, gt_phys_tval_write, },
{ "CNTP_TVAL(S)", 15,14,2, 0,0,0, 0, ARM_CP_NO_RAW | ARM_CP_IO,
PL1_RW | PL0_R, ARM_CP_SECSTATE_S, NULL, 0, 0, {0, 0},
gt_ptimer_access, gt_sec_tval_read, gt_sec_tval_write },
{ "CNTP_TVAL_EL0", 0,14,2, 3,3,0, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
gt_ptimer_access, gt_phys_tval_read, gt_phys_tval_write, NULL, NULL, gt_phys_timer_reset },
@ -1401,8 +1407,11 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
gt_vct_access, gt_virt_cnt_read, NULL, NULL, NULL, NULL },
/* Comparison value, indicating when the timer goes off */
{ "CNTP_CVAL", 15, 0,14, 0,2, 0, 0,
ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), {0, 0},
ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, ARM_CP_SECSTATE_NS, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), {0, 0},
gt_ptimer_access, NULL, gt_phys_cval_write, NULL, raw_write, NULL },
{ "CNTP_CVAL(S)", 15,0,14, 0,2,0, 0, ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
PL1_RW | PL0_R, ARM_CP_SECSTATE_S, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), {0, 0},
gt_ptimer_access, NULL, gt_sec_cval_write, NULL, raw_write },
{ "CNTP_CVAL_EL0", 0,14,2, 3,3,2, ARM_CP_STATE_AA64,
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), {0, 0},
gt_ptimer_access, NULL, gt_phys_cval_write, NULL, raw_write, },