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Add implementation of access to the ARM SPSR register. (#1178)

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The SPSR register is named within the Unicorn headers, but the code
to access it is absent. This means that it will always read as 0 and
ignore writes. This makes it harder to work with changes in processor
mode, as the usual way to return from a CPU exception is a
`MOVS pc, lr` for undefined instructions or `SUBS pc, lr, #4`
for most other aborts - which implicitly restores the CPSR from SPSR.

This change adds the access to the SPSR so that it can be read and
written as the caller might expect.

Backports commit 99097cab4c39fb3fc50eea8f0006954f62a149b2 from unicorn.
This commit is contained in:
Charles Ferguson 2020-01-14 09:57:47 -05:00 committed by Lioncash
parent 80a286cf8a
commit 0d0d054382
1 changed files with 6 additions and 0 deletions
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6
qemu/target/arm/unicorn_arm.c
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@ -75,6 +75,9 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
*(uint32_t *)value = cpsr_read(state) & mask;
break;
}
case UC_ARM_REG_SPSR:
*(int32_t *)value = state->spsr;
break;
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
*(uint32_t *)value = state->regs[13];
@ -143,6 +146,9 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
cpsr_write(state, *(uint32_t *)value, mask, CPSRWriteRaw);
break;
}
case UC_ARM_REG_SPSR:
state->spsr = *(uint32_t *)value;
break;
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
state->regs[13] = *(uint32_t *)value;