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https://github.com/yuzu-emu/unicorn.git
synced 2025-03-23 05:25:11 +00:00
target/i386/translate: Perform comparison pass against qemu
Ensure code and formatting match qemu where applicable
This commit is contained in:
parent
83b35aa797
commit
0d0dd2ba98
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@ -329,11 +329,6 @@ static void gen_update_cc_op(DisasContext *s)
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}
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}
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static void fpu_update_ip(CPUX86State *env, target_ulong pc)
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{
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env->fpip = pc;
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}
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#ifdef TARGET_X86_64
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#define NB_OP_SIZES 4
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@ -2179,7 +2174,6 @@ typedef struct AddressParts {
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target_long disp;
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} AddressParts;
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static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,
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int modrm)
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{
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@ -2242,7 +2236,6 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,
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if (base == R_ESP && s->popl_esp_hack) {
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disp += s->popl_esp_hack;
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}
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if (base == R_EBP || base == R_ESP) {
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def_seg = R_SS;
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}
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@ -2955,7 +2948,6 @@ static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
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set_cc_op(s, CC_OP_DYNAMIC);
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if (s->jmp_opt) {
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gen_goto_tb(s, tb_num, eip);
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s->base.is_jmp = DISAS_NORETURN;
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} else {
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gen_jmp_im(s, eip);
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gen_eob(s);
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@ -6097,15 +6089,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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ot = mo_b_d(b, dflag);
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modrm = x86_ldub_code(env, s);
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mod = (modrm >> 6) & 3;
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reg = ((modrm >> 3) & 7) | rex_r;
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if (mod != 3) {
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if (reg != 0)
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goto illegal_op;
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s->rip_offset = insn_const_size(ot);
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gen_lea_modrm(env, s, modrm);
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} else {
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if (reg != 0 && reg != 7)
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goto illegal_op;
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}
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val = insn_get(env, s, ot);
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tcg_gen_movi_tl(tcg_ctx, cpu_T0, val);
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@ -6486,7 +6472,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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/* fcomp needs pop */
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gen_helper_fpop(tcg_ctx, cpu_env);
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}
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fpu_update_ip(env, pc_start);
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}
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else if((op == 0x08) || /* flds */
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(op == 0x0a) || /* fsts */
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@ -6571,12 +6556,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fpop(tcg_ctx, cpu_env);
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break;
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}
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fpu_update_ip(env, pc_start);
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}
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else if(op == 0x0c) /* fldenv mem */
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_fldenv(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1));
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}
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else if(op == 0x0d) /* fldcw mem */
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@ -6587,8 +6569,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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else if(op == 0x0e) /* fnstenv mem */
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_fstenv(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1));
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}
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else if(op == 0x0f) /* fnstcw mem */
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@ -6599,29 +6579,19 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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else if(op == 0x1d) /* fldt mem */
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_fldt_ST0(tcg_ctx, cpu_env, cpu_A0);
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fpu_update_ip(env, pc_start);
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}
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else if(op == 0x1f) /* fstpt mem */
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_fstt_ST0(tcg_ctx, cpu_env, cpu_A0);
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gen_helper_fpop(tcg_ctx, cpu_env);
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fpu_update_ip(env, pc_start);
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}
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else if(op == 0x2c) /* frstor mem */
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_frstor(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1));
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}
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else if(op == 0x2e) /* fnsave mem */
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_fsave(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1));
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}
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else if(op == 0x2f) /* fnstsw mem */
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@ -6632,35 +6602,27 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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else if(op == 0x3c) /* fbld */
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_fbld_ST0(tcg_ctx, cpu_env, cpu_A0);
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fpu_update_ip(env, pc_start);
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}
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else if(op == 0x3e) /* fbstp */
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{
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_fbst_ST0(tcg_ctx, cpu_env, cpu_A0);
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gen_helper_fpop(tcg_ctx, cpu_env);
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fpu_update_ip(env, pc_start);
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}
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else if(op == 0x3d) /* fildll */
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{
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tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
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gen_helper_fildll_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64);
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fpu_update_ip(env, pc_start);
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}
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else if(op == 0x3f) /* fistpll */
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{
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gen_helper_fistll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env);
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tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
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gen_helper_fpop(tcg_ctx, cpu_env);
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fpu_update_ip(env, pc_start);
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}
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else
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{
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goto illegal_op;
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goto unknown_op;
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}
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} else {
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/* register float ops */
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@ -6681,8 +6643,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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switch(rm) {
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case 0: /* fnop */
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/* check exceptions (FreeBSD FPU probe) */
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_fwait(tcg_ctx, cpu_env);
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break;
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default:
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@ -6971,9 +6931,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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break;
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default:
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goto illegal_op;
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goto unknown_op;
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}
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fpu_update_ip(env, pc_start);
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}
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break;
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/************************/
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@ -7030,7 +6989,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_cmps(s, ot);
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}
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break;
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case 0x6c: /* insS */ // qq
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case 0x6c: /* insS */
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case 0x6d:
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ot = mo_b_d32(b, dflag);
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tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, cpu_regs[R_EDX]);
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@ -7042,7 +7001,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_ins(s, ot);
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}
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break;
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case 0x6e: /* outsS */ // qq
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case 0x6e: /* outsS */
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case 0x6f:
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ot = mo_b_d32(b, dflag);
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tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, cpu_regs[R_EDX]);
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@ -7058,8 +7017,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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/************************/
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/* port I/O */
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case 0xe4: // in
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case 0xe5: // out
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case 0xe4:
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case 0xe5:
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ot = mo_b_d32(b, dflag);
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val = x86_ldub_code(env, s);
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tcg_gen_movi_tl(tcg_ctx, cpu_T0, val);
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@ -7078,11 +7037,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_check_io(s, ot, pc_start - s->cs_base,
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svm_is_rep(prefixes));
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gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, R_EAX);
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tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, val);
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tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, cpu_T1);
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gen_helper_out_func(tcg_ctx, ot, cpu_tmp2_i32, cpu_tmp3_i32);
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gen_bpt_io(s, cpu_tmp2_i32, ot);
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break;
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case 0xec:
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case 0xed:
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@ -7707,26 +7666,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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break;
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case 0xfb: /* sti */
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if (!s->vm86) {
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if (s->cpl <= s->iopl) {
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gen_sti:
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gen_helper_sti(tcg_ctx, cpu_env);
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/* interruptions are enabled only the first insn after sti */
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/* If several instructions disable interrupts, only the
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_first_ does it */
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gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
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/* give a chance to handle pending irqs */
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gen_jmp_im(s, s->pc - s->cs_base);
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gen_eob(s);
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} else {
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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}
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if (s->vm86 ? s->iopl == 3 : s->cpl <= s->iopl) {
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gen_helper_sti(tcg_ctx, tcg_ctx->cpu_env);
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/* interruptions are enabled only the first insn after sti */
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gen_jmp_im(s, s->pc - s->cs_base);
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gen_eob_inhibit_irq(s, true);
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} else {
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if (s->iopl == 3) {
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goto gen_sti;
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} else {
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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}
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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}
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break;
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case 0x62: /* bound */
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/* For Intel SYSENTER is valid on 64-bit */
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if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
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goto illegal_op;
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if (!s->pe) {
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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} else {
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@ -9379,6 +9324,7 @@ static const TranslatorOps i386_tr_ops = {
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
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{
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DisasContext dc;
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translator_loop(&i386_tr_ops, &dc.base, cpu, tb);
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}
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@ -1549,8 +1549,8 @@ void tb_invalidate_phys_page_range(struct uc_struct *uc, tb_page_addr_t start, t
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return;
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}
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#if defined(TARGET_HAS_PRECISE_SMC)
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if (cpu != NULL) {
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env = cpu->env_ptr;
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if (uc->cpu != NULL) {
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env = uc->cpu->env_ptr;
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}
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#endif
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@ -1577,9 +1577,9 @@ void tb_invalidate_phys_page_range(struct uc_struct *uc, tb_page_addr_t start, t
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if (current_tb_not_found) {
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current_tb_not_found = 0;
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current_tb = NULL;
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if (cpu->mem_io_pc) {
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if (uc->cpu->mem_io_pc) {
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/* now we have a real cpu fault */
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current_tb = tb_find_pc(uc, cpu->mem_io_pc);
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current_tb = tb_find_pc(uc, uc->cpu->mem_io_pc);
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}
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}
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if (current_tb == tb &&
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@ -1592,7 +1592,7 @@ void tb_invalidate_phys_page_range(struct uc_struct *uc, tb_page_addr_t start, t
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current_tb_modified = 1;
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// self-modifying code will restore state from TB
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cpu_restore_state_from_tb(cpu, current_tb, cpu->mem_io_pc);
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cpu_restore_state_from_tb(uc->cpu, current_tb, uc->cpu->mem_io_pc);
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cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
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¤t_flags);
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}
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@ -1612,8 +1612,8 @@ void tb_invalidate_phys_page_range(struct uc_struct *uc, tb_page_addr_t start, t
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/* we generate a block containing just the instruction
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modifying the memory. It will ensure that it cannot modify
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itself */
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tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
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cpu_loop_exit_noexc(cpu);
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tb_gen_code(uc->cpu, current_pc, current_cs_base, current_flags, 1);
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cpu_loop_exit_noexc(uc->cpu);
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}
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#endif
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}
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