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target/arm/translate-a64: Correct bad merge
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Lioncash
parent
fabd6c7ae8
commit
0dd13de42f
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@ -1409,7 +1409,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
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gen_goto_tb(s, 0, addr);
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}
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/* Compare & branch (immediate)
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/* Compare and branch (immediate)
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* 31 30 25 24 23 5 4 0
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* +----+-------------+----+---------------------+--------+
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* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
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@ -1439,7 +1439,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
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gen_goto_tb(s, 1, addr);
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}
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/* Test & branch (immediate)
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/* Test and branch (immediate)
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* 31 30 25 24 23 19 18 5 4 0
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* +----+-------------+----+-------+-------------+------+
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* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
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@ -1975,12 +1975,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
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switch (opc) {
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case 0: /* BR */
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tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_pc, cpu_reg(s, rn));
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break;
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case 1: /* BLR */
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tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_pc, cpu_reg(s, rn));
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tcg_gen_movi_i64(tcg_ctx, cpu_reg(s, 30), s->pc);
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break;
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case 2: /* RET */
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gen_a64_set_pc(s, cpu_reg(s, rn));
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/* BLR also needs to load return address */
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@ -2064,7 +2059,6 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
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TCGMemOp memop = s->be_data;
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g_assert(size <= 3);
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if (is_pair) {
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g_assert(size >= 2);
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if (size == 2) {
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@ -2093,11 +2087,10 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
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tcg_gen_mov_i64(tcg_ctx, cpu_reg(s, rt2), tcg_ctx->cpu_exclusive_high);
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}
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} else {
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memop |= size;
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memop |= size | MO_ALIGN;
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tcg_gen_qemu_ld_i64(s->uc, tcg_ctx->cpu_exclusive_val, addr, idx, memop);
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tcg_gen_mov_i64(tcg_ctx, cpu_reg(s, rt), tcg_ctx->cpu_exclusive_val);
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}
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tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_exclusive_addr, addr);
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}
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@ -2150,7 +2143,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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size | MO_ALIGN | s->be_data);
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tcg_gen_setcond_i64(tcg_ctx, TCG_COND_NE, tmp, tmp, tcg_ctx->cpu_exclusive_val);
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}
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tcg_gen_mov_i64(tcg_ctx, cpu_reg(s, rd), tmp);
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tcg_temp_free_i64(tcg_ctx, tmp);
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tcg_gen_br(tcg_ctx, done_label);
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@ -2345,7 +2337,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
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int rt = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int rt2 = extract32(insn, 10, 5);
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uint64_t offset = sextract32(insn, 15, 7);
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uint64_t offset = sextract64(insn, 15, 7);
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int index = extract32(insn, 23, 2);
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bool is_vector = extract32(insn, 26, 1);
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bool is_load = extract32(insn, 22, 1);
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@ -2759,7 +2751,6 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
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} else {
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TCGv_i64 tcg_rt = cpu_reg(s, rt);
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bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
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if (is_store) {
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do_gpr_st(s, tcg_rt, tcg_addr, size,
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true, rt, iss_sf, false);
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@ -3494,7 +3485,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
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return;
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}
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done:
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done:
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if (!sf) { /* zero extend final result */
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tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, tcg_rd);
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}
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@ -3991,6 +3982,7 @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
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* +--+--+--+------------------------+------+---------+------+-----+
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* [000000]
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*/
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static void disas_adc_sbc(DisasContext *s, uint32_t insn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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@ -4127,6 +4119,9 @@ static void disas_cc(DisasContext *s, uint32_t insn)
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tcg_gen_and_i32(tcg_ctx, tcg_ctx->cpu_VF, tcg_ctx->cpu_VF, tcg_t2);
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}
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}
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tcg_temp_free_i32(tcg_ctx, tcg_t0);
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tcg_temp_free_i32(tcg_ctx, tcg_t1);
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tcg_temp_free_i32(tcg_ctx, tcg_t2);
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}
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/* Conditional select
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@ -4160,7 +4155,6 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
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a64_test_cc(tcg_ctx, &c, cond);
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zero = tcg_const_i64(tcg_ctx, 0);
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if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
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/* CSET & CSETM. */
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tcg_gen_setcond_i64(tcg_ctx, tcg_invert_cond(c.cond), tcg_rd, c.value, zero);
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@ -4170,7 +4164,6 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
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} else {
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TCGv_i64 t_true = cpu_reg(s, rn);
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TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
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if (else_inv && else_inc) {
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tcg_gen_neg_i64(tcg_ctx, t_false, t_false);
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} else if (else_inv) {
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@ -6649,6 +6642,10 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
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size = extract32(size, 0, 1) ? MO_64 : MO_32;
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}
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if (!fp_access_check(s)) {
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return;
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}
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fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
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break;
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default:
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@ -7107,7 +7104,6 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
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tcg_temp_free_i64(tcg_ctx, tcg_op);
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}
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tcg_temp_free_i64(tcg_ctx, tcg_shift);
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clear_vec_high(s, is_q, rd);
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} else {
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TCGv_i32 tcg_shift = tcg_const_i32(tcg_ctx, shift);
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@ -7171,6 +7167,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_ptr tcg_fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
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TCGv_i32 tcg_shift = NULL;
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TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
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int pass;
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@ -7632,7 +7629,6 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
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cond = TCG_COND_EQ;
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goto do_cmop;
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}
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/* CMTST : test is "if (X & Y != 0)". */
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gen_cmtst_i64(tcg_ctx, tcg_rd, tcg_rn, tcg_rm);
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break;
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case 0x8: /* SSHL, USHL */
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@ -8373,7 +8369,6 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
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}
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write_vec_element(s, tcg_res, rd, pass, MO_64);
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}
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tcg_temp_free_i64(tcg_ctx, tcg_res);
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tcg_temp_free_i64(tcg_ctx, tcg_zero);
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tcg_temp_free_i64(tcg_ctx, tcg_op);
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@ -8490,7 +8485,6 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
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}
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write_vec_element(s, tcg_res, rd, pass, MO_64);
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}
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tcg_temp_free_i64(tcg_ctx, tcg_res);
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tcg_temp_free_i64(tcg_ctx, tcg_op);
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clear_vec_high(s, !is_scalar, rd);
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@ -9304,7 +9298,6 @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
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.load_dest = true,
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.vece = MO_64 },
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};
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int size = 32 - clz32(immh) - 1;
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int immhb = immh << 3 | immb;
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int shift = immhb - (8 << size);
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@ -10047,6 +10040,7 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
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case 4: /* EOR */
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0);
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return;
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case 5: /* BSL bitwise select */
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gen_gvec_op3(s, is_q, rd, rn, rm, &bsl_op);
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return;
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@ -10056,6 +10050,7 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
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case 7: /* BIF, bitwise insert if false */
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gen_gvec_op3(s, is_q, rd, rn, rm, &bif_op);
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return;
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default:
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g_assert_not_reached();
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}
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@ -10719,7 +10714,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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tcg_temp_free_i32(tcg_ctx, tcg_op2);
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}
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}
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clear_vec_high(s, is_q, rd);
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}
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@ -11048,27 +11042,6 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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}
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return;
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case 0xc: /* FCADD, #90 */
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case 0xe: /* FCADD, #270 */
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rot = extract32(opcode, 1, 1);
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switch (size) {
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case 1:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
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gen_helper_gvec_fcaddh);
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break;
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case 2:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
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gen_helper_gvec_fcadds);
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break;
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case 3:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
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gen_helper_gvec_fcaddd);
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break;
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default:
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g_assert_not_reached();
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}
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return;
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case 0x8: /* FCMLA, #0 */
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case 0x9: /* FCMLA, #90 */
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case 0xa: /* FCMLA, #180 */
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@ -11092,6 +11065,27 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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}
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return;
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case 0xc: /* FCADD, #90 */
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case 0xe: /* FCADD, #270 */
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rot = extract32(opcode, 1, 1);
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switch (size) {
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case 1:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
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gen_helper_gvec_fcaddh);
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break;
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case 2:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
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gen_helper_gvec_fcadds);
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break;
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case 3:
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gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
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gen_helper_gvec_fcaddd);
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break;
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default:
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g_assert_not_reached();
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}
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return;
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default:
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g_assert_not_reached();
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}
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@ -12005,6 +11999,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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g_assert_not_reached();
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}
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/* Check additional constraints for the scalar encoding */
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if (is_scalar) {
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if (!is_q) {
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