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target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill()

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All of the callers of get_phys_addr() and arm_tlb_fill() now ignore
the FSR values they return, so we can just remove the argument
entirely.

Backports commit bc52bfeb3be2052942b7dac8ba284f342ac9605b from qemu
This commit is contained in:
Peter Maydell 2018-03-05 14:05:06 -05:00 committed by Lioncash
parent ec686af668
commit 0dfb84ea50
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 14 additions and 30 deletions
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38
qemu/target/arm/helper.c
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@ -20,7 +20,7 @@ typedef struct ARMCacheAttrs {
static bool get_phys_addr(CPUARMState *env, target_ulong address, static bool get_phys_addr(CPUARMState *env, target_ulong address,
MMUAccessType access_type, ARMMMUIdx mmu_idx, MMUAccessType access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
target_ulong *page_size, uint32_t *fsr, target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
@ -1923,7 +1923,6 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
hwaddr phys_addr; hwaddr phys_addr;
target_ulong page_size; target_ulong page_size;
int prot; int prot;
uint32_t fsr_unused;
bool ret; bool ret;
uint64_t par64; uint64_t par64;
MemTxAttrs attrs = {0}; MemTxAttrs attrs = {0};
@ -1931,7 +1930,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
ARMCacheAttrs cacheattrs = {0}; ARMCacheAttrs cacheattrs = {0};
ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
&prot, &page_size, &fsr_unused, &fi, &cacheattrs); &prot, &page_size, &fi, &cacheattrs);
/* TODO: this is not the correct condition to use to decide whether /* TODO: this is not the correct condition to use to decide whether
* to report a PAR in 64-bit or 32-bit format. * to report a PAR in 64-bit or 32-bit format.
*/ */
@ -6172,7 +6171,6 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
target_ulong page_size; target_ulong page_size;
hwaddr physaddr; hwaddr physaddr;
int prot; int prot;
uint32_t fsr;
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
if (!sattrs.nsc || sattrs.ns) { if (!sattrs.nsc || sattrs.ns) {
@ -6187,7 +6185,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
return false; return false;
} }
if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx,
&physaddr, &attrs, &prot, &page_size, &fsr, &fi, NULL)) { &physaddr, &attrs, &prot, &page_size, &fi, NULL)) {
/* the MPU lookup failed */ /* the MPU lookup failed */
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
// Unicorn: commented out // Unicorn: commented out
@ -8933,14 +8931,13 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
* @attrs: set to the memory transaction attributes to use * @attrs: set to the memory transaction attributes to use
* @prot: set to the permissions for the page containing phys_ptr * @prot: set to the permissions for the page containing phys_ptr
* @page_size: set to the size of the page containing phys_ptr * @page_size: set to the size of the page containing phys_ptr
* @fsr: set to the DFSR/IFSR value on failure
* @fi: set to fault info if the translation fails * @fi: set to fault info if the translation fails
* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
*/ */
static bool get_phys_addr(CPUARMState *env, target_ulong address, static bool get_phys_addr(CPUARMState *env, target_ulong address,
MMUAccessType access_type, ARMMMUIdx mmu_idx, MMUAccessType access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
target_ulong *page_size, uint32_t *fsr, target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{ {
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
@ -8955,7 +8952,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
ret = get_phys_addr(env, address, access_type, ret = get_phys_addr(env, address, access_type,
stage_1_mmu_idx(mmu_idx), &ipa, attrs, stage_1_mmu_idx(mmu_idx), &ipa, attrs,
prot, page_size, fsr, fi, cacheattrs); prot, page_size, fi, cacheattrs);
/* If S1 fails or S2 is disabled, return early. */ /* If S1 fails or S2 is disabled, return early. */
if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
@ -8968,7 +8965,6 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
phys_ptr, attrs, &s2_prot, phys_ptr, attrs, &s2_prot,
page_size, fi, page_size, fi,
cacheattrs != NULL ? &cacheattrs2 : NULL); cacheattrs != NULL ? &cacheattrs2 : NULL);
*fsr = arm_fi_to_lfsc(fi);
fi->s2addr = ipa; fi->s2addr = ipa;
/* Combine the S1 and S2 perms. */ /* Combine the S1 and S2 perms. */
*prot &= s2_prot; *prot &= s2_prot;
@ -9013,17 +9009,14 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
/* PMSAv8 */ /* PMSAv8 */
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
phys_ptr, attrs, prot, fi); phys_ptr, attrs, prot, fi);
*fsr = arm_fi_to_sfsc(fi);
} else if (arm_feature(env, ARM_FEATURE_V7)) { } else if (arm_feature(env, ARM_FEATURE_V7)) {
/* PMSAv7 */ /* PMSAv7 */
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
phys_ptr, prot, fi); phys_ptr, prot, fi);
*fsr = arm_fi_to_sfsc(fi);
} else { } else {
/* Pre-v7 MPU */ /* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
phys_ptr, prot, fi); phys_ptr, prot, fi);
*fsr = arm_fi_to_sfsc(fi);
} }
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n", " mmu_idx %u -> %s (prot %c%c%c)\n",
@ -9049,24 +9042,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
} }
if (regime_using_lpae_format(env, mmu_idx)) { if (regime_using_lpae_format(env, mmu_idx)) {
bool ret = get_phys_addr_lpae(env, address, access_type, mmu_idx, return get_phys_addr_lpae(env, address, access_type, mmu_idx,
phys_ptr, attrs, prot, page_size, phys_ptr, attrs, prot, page_size,
fi, cacheattrs); fi, cacheattrs);
*fsr = arm_fi_to_lfsc(fi);
return ret; return ret;
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
bool ret = get_phys_addr_v6(env, address, access_type, mmu_idx, return get_phys_addr_v6(env, address, access_type, mmu_idx,
phys_ptr, attrs, prot, page_size, fi); phys_ptr, attrs, prot, page_size, fi);
*fsr = arm_fi_to_sfsc(fi);
return ret;
} else { } else {
bool ret = get_phys_addr_v5(env, address, access_type, mmu_idx, return get_phys_addr_v5(env, address, access_type, mmu_idx,
phys_ptr, prot, page_size, fi); phys_ptr, prot, page_size, fi);
*fsr = arm_fi_to_sfsc(fi);
return ret;
} }
} }
@ -9075,7 +9060,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
* fsr with ARM DFSR/IFSR fault register format value on failure. * fsr with ARM DFSR/IFSR fault register format value on failure.
*/ */
bool arm_tlb_fill(CPUState *cs, vaddr address, bool arm_tlb_fill(CPUState *cs, vaddr address,
MMUAccessType access_type, int mmu_idx, uint32_t *fsr, MMUAccessType access_type, int mmu_idx,
ARMMMUFaultInfo *fi) ARMMMUFaultInfo *fi)
{ {
CPUARMState *env = cs->env_ptr; CPUARMState *env = cs->env_ptr;
@ -9087,7 +9072,7 @@ bool arm_tlb_fill(CPUState *cs, vaddr address,
ret = get_phys_addr(env, address, access_type, ret = get_phys_addr(env, address, access_type,
core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
&attrs, &prot, &page_size, fsr, fi, NULL); &attrs, &prot, &page_size, fi, NULL);
if (!ret) { if (!ret) {
/* Map a single [sub]page. */ /* Map a single [sub]page. */
phys_addr &= TARGET_PAGE_MASK; phys_addr &= TARGET_PAGE_MASK;
@ -9109,12 +9094,11 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
target_ulong page_size; target_ulong page_size;
int prot; int prot;
bool ret; bool ret;
uint32_t fsr;
ARMMMUFaultInfo fi = {0}; ARMMMUFaultInfo fi = {0};
ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
attrs, &prot, &page_size, &fsr, &fi, NULL); attrs, &prot, &page_size, &fi, NULL);
if (ret) { if (ret) {
return -1; return -1;