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target/riscv: floating-point scalar move instructions

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Backports 2843420a562c107801bae20f74579e4fe540316f
This commit is contained in:
LIU Zhiwei 2021-03-07 12:41:21 -05:00 committed by Lioncash
parent b75de9504c
commit 0e0ac052cd
2 changed files with 56 additions and 0 deletions
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3
qemu/target/riscv/insn32.decode
View file

@ -72,6 +72,7 @@
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
@r2rd ....... ..... ..... ... ..... ....... %rs2 %rd
@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@ -565,6 +566,8 @@ viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

53
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -2762,3 +2762,56 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
}
return false;
}
/* Floating-Point Scalar Move Instructions */
static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!s->vill && has_ext(s, RVF) &&
(s->mstatus_fs != 0) && (s->sew != 0)) {
unsigned int len = 8 << s->sew;
vec_element_loadi(s, tcg_ctx->cpu_fpr_risc[a->rd], a->rs2, 0);
if (len < 64) {
tcg_gen_ori_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rd],
MAKE_64BIT_MASK(len, 64 - len));
}
mark_fs_dirty(s);
return true;
}
return false;
}
/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
TCGv_i64 t1;
/* The instructions ignore LMUL and vector register group. */
uint32_t vlmax = s->vlen >> 3;
/* if vl == 0, skip vector register write back */
TCGLabel *over = gen_new_label(tcg_ctx);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over);
/* zeroed all elements */
tcg_gen_gvec_dup_imm(tcg_ctx, SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
/* NaN-box f[rs1] as necessary for SEW */
t1 = tcg_temp_new_i64(tcg_ctx);
if (s->sew == MO_64 && !has_ext(s, RVD)) {
tcg_gen_ori_i64(tcg_ctx, t1, tcg_ctx->cpu_fpr_risc[a->rs1], MAKE_64BIT_MASK(32, 32));
} else {
tcg_gen_mov_i64(tcg_ctx, t1, tcg_ctx->cpu_fpr_risc[a->rs1]);
}
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(tcg_ctx, t1);
gen_set_label(tcg_ctx, over);
return true;
}
return false;
}