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target-mips: assorted formatting fixes

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Backports commits d75de74967f631a7d0b538d4b88f96f9c426bfe2, 6225a4a0e39cb24e7b9e1d4d2c1a3e6eaee18e85, and d2bfa6e6222baa0218bd0658499d38bac56ac34c from qemu
This commit is contained in:
Maciej W. Rozycki 2018-02-11 16:00:43 -05:00 committed by Lioncash
parent ca496991ea
commit 0f82a7f89f
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 34 additions and 32 deletions
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14
qemu/target-mips/translate.c
View file

@ -11196,7 +11196,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case M16_OPC_LD: case M16_OPC_LD:
check_mips_64(ctx); check_mips_64(ctx);
gen_ld(ctx, OPC_LD, ry, rx, offset); gen_ld(ctx, OPC_LD, ry, rx, offset);
break; break;
#endif #endif
@ -18515,7 +18515,7 @@ static void hook_insn(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patc
} }
} }
static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch, int *insn_patch_offset) static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch, int *insn_patch_offset)
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
@ -18684,7 +18684,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_di(tcg_ctx, t0, tcg_ctx->cpu_env); gen_helper_di(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, rt); gen_store_gpr(tcg_ctx, t0, rt);
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched
the execution mode */
ctx->bstate = BS_STOP; ctx->bstate = BS_STOP;
break; break;
case OPC_EI: case OPC_EI:
@ -18692,7 +18693,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env); gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, rt); gen_store_gpr(tcg_ctx, t0, rt);
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched
the execution mode */
ctx->bstate = BS_STOP; ctx->bstate = BS_STOP;
break; break;
default: /* Invalid */ default: /* Invalid */
@ -18899,8 +18901,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_S_FMT: case OPC_S_FMT:
case OPC_D_FMT: case OPC_D_FMT:
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
(imm >> 8) & 0x7); rt, rd, sa, (imm >> 8) & 0x7);
break; break;
case OPC_W_FMT: case OPC_W_FMT:
case OPC_L_FMT: case OPC_L_FMT:

52
qemu/target-mips/translate_init.c
View file

@ -861,33 +861,33 @@ static const mips_def_t mips_defs[] =
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
"Loongson-2F", "Loongson-2F",
0x6303, 0x6303,
/*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
(0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
(0x1<<4) | (0x1<<1), (0x1<<4) | (0x1<<1),
/* Note: Config1 is only used internally, Loongson-2F has only Config0. */ /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
(1 << CP0C1_FP) | (47 << CP0C1_MMU), (1 << CP0C1_FP) | (47 << CP0C1_MMU),
0, 0,
0, 0,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
0, 0,
16, 16,
2, 2,
0xF5D0FF1F, /*bit5:7 not writable*/ 0xF5D0FF1F, /*bit5:7 not writable*/
0, 0,
0, 0,
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV), (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0, 0,
40, 40,
40, 40,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_LOONGSON2F, CPU_LOONGSON2F,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
/* A generic CPU providing MIPS64 ASE DSP 2 features. /* A generic CPU providing MIPS64 ASE DSP 2 features.